Master slice LSI with integrated fault detection circuitry

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor

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G01R 3100

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057291268

ABSTRACT:
A master slice LSI with fault detection circuitry includes a packed transistor area consisting of rows of semiconductor devices packed on a substrate. Parts of the rows are used for providing an application specific integrated circuit (ASIC). Remaining parts of the rows are used for providing fault detection circuitry for finding faulty semiconductor devices. The fault detection circuitry includes shift registers, sense amplifiers, and a decoder. The detection circuitry is provided only for those rows of semiconductor devices used for providing the intended purpose ASIC.

REFERENCES:
patent: 4601034 (1986-07-01), Sridhar
Sridhar et al; "Design of Easily Testable Bit Sliced Systems"; IEEE Transactions on Computers, vol. C-30, No. 11, Nov. 1981, pp. 842-854.
McChiskey et al; "Design For Autonomous Test"; IEEE transactions on Computers, vol. 30, No. 11, Nov. 1981; pp. 866-875.
Tsui; "On Wafer and On Module Chip Testing"; IBM Technical Disclosure Bulletin, vol. 28, No. 8, Jan. 1984; pp. 4312-4323.
Tsui; "In Situ Testability Design (ISTD)--A New Approach for Testing High Speed LSI/VLSI logic"; Proceedings of the IEEE, vol. 70, No. 1, Jan. 1982; pp. 59-78.

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