Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays
Reexamination Certificate
1997-05-20
2001-08-07
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
C257S206000, C257S208000
Reexamination Certificate
active
06271548
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device employing a master slice layout in which a plurality of gate basic cells are formed previously on an LSI chip and then only a wiring design is added to construct desired logic circuits, and to a configuration of a semiconductor device and a layout design thereof capable of improving miniaturization of wiring patterns and integration density.
2. Description of the Prior Art
Various layout designs for a semiconductor integrated circuit may be prepared according to a scale of the integrated circuit and design approach. A fully-custom IC in which all layers are designed and manufactured for exclusive use is suited for the case where a large number of high performance ICs are to be manufactured. In contrast, a semicustom IC such as Application-Specific Integrated Circuits (ASICs) in which layers located below a wiring layer level are manufactured in advance and then only wiring layers are designed and manufactured is suited for the case where specific-application ICs are to be manufactured in a short term. In addition, the semicustom IC has such an advantage that design cost and production cost can be reduced. Such ASIC is also called a gate array or master slice layout. An example of the basic cell layout of the semiconductor integrated circuit of this type is shown in FIG.
1
A.
The layout shown in
FIG. 1A
is composed of two gate basic cells
3
a
,
3
b
and substrate/contact regions
4
a
,
4
b
formed between the gate basic cells
3
a
,
3
b
. Respective gate cells
3
a
,
3
b
are composed of two source/drain diffusion regions
12
,
14
and four gate polysilicon regions
11
. In
FIG. 1A
, for example, if a two-input NAND gate is to be formed, the gate basic cells
3
a
,
3
b
comprising two n-MOS transistors
1
a
,
1
b
and two p-MOS transistors
2
a
,
2
b
respectively are arranged on the upper and lower sides to put the substrate/contact regions
4
a
,
4
b
therebetween, whereby constituting one block. In
FIG. 1A
, in a wiring channel grid serving as a basis when the wiring layers are designed, for instance, twelve lines X
0
to X
11
are specified in the X direction and seven lines Y
0
to Y
6
are specified in the Y direction.
In the layout of the gate basic cell in which the wiring channel grid is specified in this manner, as shown in a functional block layout pattern in
FIG. 1B
, for example, four-input (A, B, C, D) one-output (Z output) NAND gate is constructed by designing the layout of the wirings of the transistors
1
a
,
1
b
,
2
a
,
2
b
with the use of vertical metal wirings (VDD (higher potential) power supply wiring
5
a
, and VSS (lower potential) power supply wiring
5
b
) and a lateral metal wiring (connection wiring
6
).
In the prior art, in the layout of the gate basic cell, pitches of the wiring channel grid are defined as a uniform value or defined uniformly in the X and Y directions respectively to make much account of its matching to layout CAD. Design values of the pitches of the wiring channel grid are defined according to a logical product of design rules in regions in which functional blocks are formed and wiring regions. Hence, the pitches of the wiring channel grid must be made narrower with the progress of miniaturization.
Meanwhile, in the technical field of the semiconductor integrated circuit, development of the LSI is entering the region called deep submicron generation or sub-quartermicron generation according to the progress of fine pattern techniques. In these generations, harmful influences due to miniaturization have become dominant. For example, it has become an issue that, according to miniaturization of the power supply metal wiring, generation of electromigration and/or source voltage drop of the transistors due to resistance of wiring material exert harmful influences upon an operation of the device. For this reason, the advance of miniaturization of the line width of the metal wiring has been slowed down after the middle of the 1980s compared to miniaturization of the gate length of the transistor. In addition, since contact resistance is increased because of miniaturization of the area of the contact hole, source voltage drop of the transistors has also been caused to thus exert harmful influences upon an operation speed of the device.
For the above reasons, it may be supposed that the line width of the power supply metal wiring is restricted to technological limits such as almost 0.3 to 0.5 &mgr;m because of resistance value of material unless a room-temperature superconducting wiring is employed, and therefore it appears that miniaturization of the power supply metal wiring is at a critical stage. In particular, it has been said that miniaturization can be improved at most to the ⅔ extent of the present miniaturization even if Ag, Au, Cu, etc. whose resistance values are lower than Al being mainly used at present are employed. In other words, it is possible that wirings other than the power supply metal wiring can be further miniaturized, but it has become difficult to improve the integration density by using the conventional wiring channel grid having uniform pitches since the line width of the power supply metal wiring, etc. determine the design rule.
In the case that the pitches of the wiring channel grid are designed, two cases may be considered if classified broadly.
(i) One case is that only the design rule for the wiring process, i.e., wiring width and wiring interval, contact hole size and contact hole interval, via hole contact size and via hole contact interval in the multilevel wirings, etc. must be considered.
(ii) The other case is that design rules in fabrication stages prior to the wiring process must be considered. Namely, design rule for manufacturing process of the basic cell (basic cell process) in addition to the design rule for the wiring process must be considered to design the pitches of the wiring channel grid. In the following, early processes such as oxidation, CVD, ion implantation, RIE, etc. performed until the interlayer insulating film just under the bottom metal layer are formed, including patterning of the gate polysilicon of the basic cell, will be called “basic cell process”. And the process after forming the interlayer insulating film, such as opening the contact holes in the interlayer insulating film and patterning the wiring layers will be called wiring process”.
In the layout of the gate basic cell shown in
FIG. 1A
, only the design rule for the wiring process should be regarded in order to define pitches of the lines X
1
-X
2
-X
3
-X
4
, X
7
-X
8
-X
9
-X
10
constituting the wiring channel grid. This corresponds to the case (i). In contrast, the design rules for contact margin allocated to the polysilicon regions
11
, intervals between the polysilicon regions
11
and the source/drain regions
12
,
14
, and contact margin allocated to the source/drain regions
12
,
14
should also be regarded-in order to define the pitches of the lines X
0
-X
1
, X
4
-X
5
, X
6
-X
7
, X
10
-X
11
constituting the wiring channel grid. This corresponds to the case (ii). Similarly, the design rules for contact margin allocated to the polysilicon regions
11
and intervals between the polysilicon regions
11
should be regarded in order to define the pitches of the lines X
5
-X
6
, X
11
-X
0
constituting the wiring channel grid. Further, in order to define the pitches of two sets of lines Y
0
-Y
1
-Y
2
, Y
4
-Y
5
-Y
6
, the design rule for contact margin allocated to the gate polysilicon regions
11
or intervals between the contact holes for the source/drain regions
12
,
14
and the narrowest portion of the polysilicon region defining a gate length of the MOSFET should be regarded in addition to the design rule for the wiring process. In order to define the pitches of a set of lines Y
2
-Y
3
-Y
4
, the design rule for intervals between the source/drain regions
12
,
14
and the substrate/contact regions
4
a
,
4
b
in addition to the design rule for the wiring process shou
Maeno Muneaki
Sei Toshikazu
Uchino Yukinori
Umemoto Yasunobu
Cao Phat X.
Chaudhuri Olik
Foley & Lardner
Kabushiki Kaisha Toshiba
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