Master slice integrated circuit having high and low speed unit c

Details Master slice integrated circuit having high and low speed unit c Master slice integrated circuit having high and low speed unit c

1988-08-15

1990-05-01

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307455, 307467, 307591, 357 45, H03K 19013, H03K 19177

Patent

active

049221361

ABSTRACT:
A semiconductor integrated circuit of the master slice system is formed by arranging internal cell groups of different operating speeds in the form of arrays respectively. The internal cell groups of different operating speeds can be interconnected with each other through internal connecting areas, to reduce power consumption. The structure of each internal cell group can be optimized in accordance with its operating speed, so that the entire formation area is not much increased. Further, the formation ratio of the internal cell groups of different operating speeds is so appropriately set as to improve availability thereof.

REFERENCES:
patent: 4438353 (1984-03-01), Sano et al.
patent: 4490630 (1984-12-01), Freeman
patent: 4527079 (1985-07-01), Thompson
patent: 4682202 (1987-07-01), Tanizawa
patent: 4742383 (1988-05-01), Fitzgerald
patent: 4760289 (1988-07-01), Eichelberger et al.
patent: 4780846 (1988-10-01), Tanabe et al.
patent: 4811073 (1989-03-01), Kitamura et al.
"Hardware of ACOS System 1500 Series", NEC Technical Information.
"A 50 PS 7K-Gate Masterslice Using Mixed-Cells Consisting of an NTL Gate and an LCML Macrocell" IEEE 1986 Custom Integrated Circuits Conference, pp. 580-583.
"An ECL 5000-Gate Array with 190-ps Gate Delay" IEEE Journal of Solid-State Circuits, vol. sc-21, No. 2, Apr. 1986.

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