Master-slice integrated circuit having an improved arrangement o

Details Master-slice integrated circuit having an improved arrangement o Master-slice integrated circuit having an improved arrangement o

1987-06-19

1988-09-13

Edlow, Martin H.

357 42, 357 41, H01L 2710, H01L 2715, H01L 2702

Patent

active

047713275

ABSTRACT:
A gate-array device has a plurality of basic cell lines in the central portion of a semiconductor chip and a plurality of I/O cells at its peripheral portion, the basic cell lines being composed of a plurality of basic cells in which at least one P-channel MOS FET and at least one N-channel MOS FET are disposed in a direction perpendicular to the basic cell lines. In each of the basic cell lines, a predetermined number of P-channel MOS FET's and the predetermined number of N-channel MOS FET's are alternatively disposed in a direction in parallel to the basic cell lines.

REFERENCES:
patent: 4161662 (1979-07-01), Malcolm et al.
patent: 4319342 (1982-03-01), Scheverlein
patent: 4412237 (1983-10-01), Matsumura et al.
patent: 4668972 (1987-05-01), Sato et al.
patent: 4682201 (1987-07-01), Lipp

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