Master slice integrated circuit having a reduced chip size and a

Details Master slice integrated circuit having a reduced chip size and a Master slice integrated circuit having a reduced chip size and a

1993-04-01

1995-06-06

Picard, Leo P.

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

174268, 361767, 361794, H05K 100

Patent

active

054224411

ABSTRACT:
In a master slice integrated circuit, a number of connection pads are located in a peripheral edge region of a chip in such a manner that each one power supply pad is interposed between each pair of signal input/output pads and a number of unitary pad arrays each of which consists of a signal pad, a power supply pad and another signal pad located in the named order are repeatedly arranged along a peripheral edge of the chip. Thus, the pad pitch can be reduced to two thirds of the width of an I/O cell, without changing the I/O cell size. In addition, since the power supply pad is located adjacent each of the I/O cells, it is effective to suppress or minimize the power supply voltage noise caused by the simultaneous driving.

REFERENCES:
patent: 4660174 (1987-04-01), Takemae et al.
patent: 4809029 (1989-02-01), Matsumura et al.
patent: 5019889 (1991-05-01), Yoshio et al.
patent: 5038192 (1991-08-01), Bonneau et al.
patent: 5153698 (1992-10-01), Hirabayashi et al.

Affiliated with

Also associated with

Rating

Master slice integrated circuit having a reduced chip size and a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Master slice integrated circuit having a reduced chip size and a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Master slice integrated circuit having a reduced chip size and a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-988651