Master slice integrated circuit having a memory region

Details Master slice integrated circuit having a memory region Master slice integrated circuit having a memory region

1991-04-26

1992-12-15

Wojciechowicz, Edward J.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

365 63, H01L 2710, G11C 506

Patent

active

051722100

ABSTRACT:
A gate array chip (33) has an array (41) of strip-shaped active areas (18) formed on a semiconductor substrate (40). Wiring-dedicated areas (34), each having capacity for two to four wires, are provided between respective adjacent pairs of the active areas (18). In a logic circuit region, one or more active areas (18) are employed as wiring areas. In memory blocks, wiring is performed by employing only the wiring-dedicated areas (34). A master slice integrated circuit manufactured from the gate array chip (33) has a high degree of integration and high operating speed.

REFERENCES:
patent: 4623911 (1986-11-01), Pryor
patent: 4783692 (1988-11-01), Unutani
patent: 4951111 (1990-08-01), Yamamoto
IEEE Journal of Solid State Circuits, vol. SC-20, No. 5 Oct. 1985, A 240K Transistor CMOS Array with Flexible Allocation of Memory and Channels, Horomasa Takahashi et al.

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