Master slice integrated circuit having a memory region

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

365 63, H01L 2710, G11C 506

Patent

active

051722100

ABSTRACT:
A gate array chip (33) has an array (41) of strip-shaped active areas (18) formed on a semiconductor substrate (40). Wiring-dedicated areas (34), each having capacity for two to four wires, are provided between respective adjacent pairs of the active areas (18). In a logic circuit region, one or more active areas (18) are employed as wiring areas. In memory blocks, wiring is performed by employing only the wiring-dedicated areas (34). A master slice integrated circuit manufactured from the gate array chip (33) has a high degree of integration and high operating speed.

REFERENCES:
patent: 4623911 (1986-11-01), Pryor
patent: 4783692 (1988-11-01), Unutani
patent: 4951111 (1990-08-01), Yamamoto
IEEE Journal of Solid State Circuits, vol. SC-20, No. 5 Oct. 1985, A 240K Transistor CMOS Array with Flexible Allocation of Memory and Channels, Horomasa Takahashi et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Master slice integrated circuit having a memory region does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Master slice integrated circuit having a memory region, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Master slice integrated circuit having a memory region will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2097738

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.