Master slice integrated circuit device

Details Master slice integrated circuit device Master slice integrated circuit device

1990-09-10

1992-10-06

James, Andrew J.

357 68, 357 71, H01L 2710, H01L 2715

Patent

active

051536986

ABSTRACT:
In a master slice integrated circuit device composed of an array of internal cells having contact members, an array of external cells having contact members and formed outwardly from the internal cell array, a main power circuit region formed on the external cell array, a plurality of power lines formed on the internal array region, and a plurality of signal lines for electrically interconnecting selected contact members of the internal and external cells, intermediate power line connection regions are provided to conductively connect each power line to the main power circuit region, the intermediate connection regions including, for each power line, a power branch-off member disposed at a given position on the main power circuit region and extending substantially in the direction of its respective power line, and a connection allowance member intersecting, and connected to, the power branch-off member and having a predetermined length, the connection allowance member being conductively connected between its associated power branch-off member and the respective power line.

REFERENCES:
patent: 4523106 (1985-06-01), Tanizawa et al.
patent: 4611236 (1986-09-01), Sato
patent: 4811073 (1989-03-01), Kitamura et al.
patent: 4833520 (1989-05-01), Ito et al.
"Master Image Layout with Macro Capability" IBM Tech Disc Bull vol. 28, No. 11, Apr. 1986 pp. 4717-4718.

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