Master slice CMOS array having complementary columns

Details Master slice CMOS array having complementary columns Master slice CMOS array having complementary columns

1990-05-10

1991-10-01

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307465, 307481, 365104, H03K 19177

Patent

active

050536486

ABSTRACT:
A master slice semiconductor integrated circuit comprising ROM memory cells which consist of NMOS-transistors as well as PMOS-transistors. In order to increase the integration density on the master slice, the NMOS-transistors and the PMOS-transistors (memory cells) in one and the same row are controlled via one and the same word line. The circuit includes row selection means, for example, an exclusive-OR circuit for each row, for selecting either a single row of NMOS cells or a single row of PMOS cells.

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patent: 4899308 (1990-02-01), Khan
"Dense ROM Architecture for CMOS Gate Arrays", IBM T.D.B., vol. 31, No. 1, Jun. 1988, pp. 125-126.
Kelly et al., "Dual-Gate Programmable Logic Array", I.B.M. T.D.B., vol. 17, No. 10, Mar. 1975, pp. 2957-2958.

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