Master-slave type flip-flop circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307279, 307289, 307291, H03K 3289, H03K 329

Patent

active

051401797

ABSTRACT:
A master-slave type flip-flop circuit with first and second transmission gates receives an input pulse signal and an inverted input pulse signal at a data input terminal and an inverted data input terminal, respectively, and receives a clock signal at a common clock input terminal. A first data holding section includes first and second inverters and first and second resistors cross-connected between input and output terminals of the first and second inverters for receiving outputs of the first and second transmission gates at the input terminals of the first and second inverters. Third and fourth transmission gates receive outputs of the first and second inverters, respectively, of the data holding section and further receive an inverted clock signal at a common inverted clock input terminal. A second holding data section includes third and fourth inverters and third and fourth resistors cross-connected between input and output terminals of the third and fourth inverters fro receiving output of the third and fourth transmission gates at the input terminals of the third and fourth inverters, respectively, The flip-flop circuit is reduced in total number of inverters and hence in power consumption and further reduced in number of inverters on a signal transmission line to permit high-speed operation. Where first to fourth capacitors are connected in parallel to the first to fourth resistors, respectively, the speed of charging and discharging of gate capacity of the transmission gates can be raised to assure a higher maximum operating frequency.

REFERENCES:
patent: 3042815 (1960-05-01), Campbell, Jr.
patent: 3573509 (1971-04-01), Crawford
patent: 4057741 (1977-11-01), Piguet
patent: 4939384 (1990-07-01), Shikata et al.
M. Tsunotani et al., "Advanced Self-Alignment Process Technique with Very Thick Sidewall for High Speed GaAs LSIs", Dec. 1988, pp. 700-703, IEDM Tech. Digest.
Malcolm E. Goodge, "Semiconductor Device Technology", 1983, pp. 240-244.

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