Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-05-20
2001-06-05
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S203000
Reexamination Certificate
active
06242957
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to flip-flop logic circuits, and more particularly to master-slave type flip-flops.
BACKGROUND OF THE INVENTION
Master-slave flip-flop circuits (MS-FFs) are known in the art. A conventional MS-FF typically includes a master latch and a slave latch connected in series with one another. A data signal (D) can be applied at a data input, and the master latch can read in and latch the data synchronously with an applied clock signal. After the master latch has operated (i.e., latched the data), the slave latch can latch a value output from the master latch. The output of the slave latch is provided as an output signal Q.
To accomplish their respective latching operations, a master latch and slave latch can be provided with a input transfer gates that function in response to certain clock signals. One way to generate clock signals is to apply a clock signal to a first inverter circuit to generate an inverted clock signal. The inverted clock signal can then be applied to a second inverter to generate a non-inverted clock signal. The inverted and non-inverted clock signals can be used to activate the transfer gates within the MS-FF and thereby allow values to be latched in the master and slave latches.
Ideally, a MS-FF operates by a master latch storing a logic value and the slave latch providing a logic value. The logic value in the master and slave latches may be the same or may be different according to the timing of clock signals. Values in the master latch can be changed by applying a new logic value to the master latch, and then clocking the new value into the master latch. The master latch will then store a new value, while the slave latch, ideally, continues to provide its logic value as an output. Subsequently, the master latch value can be clocked into the slave latch.
One way to accomplished the above clocking operation is provide a master input transfer gate at the input of the master latch, and a slave input transfer gate at the input of the slave latch. The master input transfer gate can be activated in response to a non-inverted clock signal while the slave input transfer gate can be activated in response to an inverted clock signal, or vice versa.
A drawback to the arrangement described above can arise out of delays introduced by the inverter used to generate the inverted and non-inverted clock signals. Due to such delays, the slave input transfer gate may not be sufficiently turned off prior to the master input transfer gate being turned on. Consequently, a data value applied at the input to the master latch can flow through the master latch to the slave latch. In the event the newly applied data value differs from the previous value latched by the master latch, the “through phenomenon” of the newly applied data value can result in an erroneous logic value being latched in the slave latch.
One approach to preventing the through phenomenon in a MS-FF is to generate clock signals that clock in data from a master latch to a slave latch at an earlier point of time than new data is clocked into the master latch. Such an approach is described in Japanese laid-open publication Kokkai Hei 3-1608. In this technique, even if newly applied data passes through the master latch, the slave input transfer gate will already be sufficiently turned off, and the slave latch will not accept the newly applied data. Hence, an erroneous operation as described above can be prevented.
The approach described by Japanese laid-open publication Kokkai Hei 3-1608 utilizes a first set of inverted and non-inverted clock signals that are applied to a transfer gate at the input of a slave latch. In addition, third and fourth inverter circuits are provided that generate a second set of inverted and non-inverted clock signals. The second set of inverted and non-inverted clock signals is supplied to a transfer gate at the input of a master latch. The delay introduced by the third and fourth inverter circuits makes it possible to safely store data in the slave latch before new data is stored in the master latch.
One drawback to the approach above is that in order to obtain a delay between pairs of clock signals, additional inverter circuits (the third and fourth inverter circuits) are used. The addition of the inverter circuits can result in additional area for the overall MS-FF circuit, as the circuit elements (e.g., transistors) that may be used to form the inverters are typically created in the substrate of an integrated circuit. While it is possible to utilize only one inverter circuit (e.g., only a third inverter circuit) to generate the desired clock signals, such an arrangement can still result in additional area for the MS-FF. Because smaller sized integrated circuits continues to be an on-going goal, small sized MS-FFs are desirable.
In addition to having larger area requirements, conventional MS-FFs that include delayed clock signals may still have drawbacks at higher frequencies due to parasitic resistance within the circuit. Parasitic resistance is the resistance inherent in the physical structures included in a MS-FF. As just a few examples, conductive lines, contact structures, and active devices can introduce parasitic resistance. Conductive lines can include those patterned over a substrate as well as portions of a substrate, such as “underpasses.” Contact structures can include contacts that extend from a conductive layer to a substrate, or “vias” that connect two conductive layers. Active devices, such as the source-drain path of a field effect transistor, or collector-emitter path of a bipolar transistor, can also include a parasitic resistance when the transistor is turned on.
Even in a case where a MS-FF has been designed to delay the timing of clock signals by a particular delay time, the operation of transfer gates may result in timing errors due to parasitic resistance. A master input transfer gate may require a relatively long setting time to input new data into a master latch. In addition, a slave input transfer gate may also require a relatively long setting time to input master latch data into a slave latch. Thus, it can be difficult to realize a stable operation at a high frequency.
It would be desirable to provide a MS-FF that avoids the use of additional inverter circuits and can provide stable operation for the latches within the MS-FF. It would also be desirable to provide a MS-FF that can operate at higher frequencies.
SUMMARY OF THE INVENTION
The present invention includes a master-slave flip-flop (MS-FF) having a master input transfer gate coupled to the input of a master latch and a slave input transfer gate coupled to the input of a slave latch. Also included is a clock generating circuit that provides a clock signal to the master input transfer gate and a slave input transfer gate. The clock signal is coupled to the master input transfer gate by a clock line having a parasitic resistance.
According to one embodiment, a clock generating circuit receives a clock signal as a non-inverted clock signal and includes a first inverter that generates an inverted clock signal. The non-inverted and inverted clock signals are provided to a slave input transfer gate. The non-inverted and inverted clock signals are further provided to a master input transfer gate with clock lines that include a parasitic resistance.
According to another embodiment, a clock supply circuit includes a first inverter that generates an inverted clock signal and a second inverter that generates a non-inverted clock signal. The non-inverted and inverted clock signals are provided to a slave input transfer gate. The non-inverted and inverted clock signals are further provided to a master input transfer gate with clock lines that include a parasitic resistance.
According to the embodiments, when a clock signal is input to a MS-FF, a slave input transfer gate can be turned off or on earlier, and a master input transfer gate can be turned off or on later, due to a delay introduced by parasitic resistance in clock signal lines. In this way, data can be l
Lam Tuan T.
NEC Corporation
Walker Darryl G.
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