Master/slave sequencing processor

Boots – shoes – and leggings

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Details

3642289, 3642304, 36423221, 3642431, 3642624, 3642712, G06F 1516

Patent

active

050364537

ABSTRACT:
An array processor includes a master array controller and sequencer (12) and a plurality of slave processors (20a)-(20n). The master generates sequencing commands for sequencing instruction flow in each of the slave processors. The slave processors generate addresses for associated memories (34a)-(34n). The data outputs of the memories are interfaced through a cross point switch (22) to a slave data processor (24). The master (12) is operable to initialize all of the slave devices to a starting address for an internal routine and sequence the instruction flow therein in a synchronous and parallel manner to execute a particular task.

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