Master-slave microprocessor control circuit

Details Master-slave microprocessor control circuit Master-slave microprocessor control circuit

1984-04-11

1986-12-30

Shaw, Gareth D.

Telephonic communications

Diagnostic testing, malfunction indication, or electrical...

Monitoring

379269, 379279, H04Q 900

Patent

active

046330399

ABSTRACT:
A control circuit, for use in a telephone switching system, which monitors, controls and transfers data to and from memory, input-output devices and external circuits. A pair of microprocessors and associated read-only and random-access memories are operated in a master-slave arrangement. A comparison circuit continuously monitors the integrity of the master microprocessor by comparing the signal on its data, address and control leads with those of a slave microprocessor.

REFERENCES:
patent: 3517171 (1970-06-01), Avizienis
patent: 3820085 (1974-06-01), Zelinski
patent: 3838261 (1974-09-01), Rice et al.
patent: 3845425 (1974-10-01), Clements et al.
patent: 3916384 (1975-10-01), Fleming et al.
patent: 3980839 (1976-09-01), Hutcheson
patent: 4017840 (1977-04-01), Schild et al.
"Fault-Tolerant Design of Local ESS Processors", W. N. Toy Proceedings of the IEEE, vol. 66, No. 10, Oct. 1978, pp. 1126-1145.

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