Master-slave flip-flop circuits

Details Master-slave flip-flop circuits Master-slave flip-flop circuits

1979-05-14

1981-12-01

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307288, 307362, 328206, H03K 3289

Patent

active

043038387

ABSTRACT:
A d.c. triggered master-slave flip-flop circuit including a master flip-flop with a capacitive delay means at its input, and a slave flip-flop having its input connected to the output of the master flip-flop. A capacitive delay means is connected at the input of the slave flip-flop. The slave flip-flop controls the connections at the input of the master flip-flop in known manner. The two capacitive delay means, serve to make each flip-flop circuit immune to noise pulses and also eliminate multiple triggering caused by contact bounce when the circuit is controlled by mechanical contacts.

REFERENCES:
patent: 3622810 (1971-11-01), Sasaki
patent: 3818250 (1974-06-01), Reed et al.
patent: 4188547 (1980-02-01), Fox

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