Master-slave flip-flop circuit with three phase clocking

Details Master-slave flip-flop circuit with three phase clocking Master-slave flip-flop circuit with three phase clocking

1988-02-29

1989-06-27

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 307279, 307481, 377 79, 377117, H03K 3284, H03K 326, H03K 2116

Patent

active

048432547

ABSTRACT:
A master-slave flip-flop circuit includes a master circuit switching element controlled by a first clock signal for controlling transfer of data from an input terminal to a master circuit data holding element which holds data transferred through the master circuit switching element, and a slave circuit switching element controlled by a second clock signal for controlling transfer of data from the master circuit data holding element to a slave circuit data holding element which holds data transferred through the slave circuit switching element. The first clock signal is nearly in phase with, but lags a little behind, the second clock signal.

REFERENCES:
patent: 3993916 (1976-11-01), Copeland, III et al.
patent: 4420695 (1983-12-01), Fisher
patent: 4495628 (1985-01-01), Zasio
patent: 4540903 (1985-09-01), Cooke et al.
patent: 4667339 (1987-05-01), Tubbs et al.
"Fundamentals of Semiconductor Integrated Circuits", Japan-Feb. 20, 1986, Published by Baifukan, p. 267.
Principles of CMOS VLSI Design, p. 213; Addison-Wesley Publishing Company, 1985.

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