Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2003-02-05
2004-03-30
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S203000, C327S544000
Reexamination Certificate
active
06714060
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a master slave flip-flop circuit in which consumed electric power is reduced.
2. Description of Related Art
FIG. 7
is a constitutional view of a conventional master slave flip-flop circuit. In
FIG. 7
,
21
indicates a clock input driver for receiving a clock signal CLK, outputting a positive phase clock signal T having the same phase as that of the clock signal CLK and outputting an inverted phase clock signal TC having a phase opposite to that of the clock signal CLK.
22
indicates a master latch circuit set to a data though state in response to the low level of the clock signal CLK and set to a data holding state in response to the high level of the clock signal CLK to load a new value of a data signal D in each data though state and to hold the new value in the data holding state set just after the data though state.
23
indicates a slave latch circuit set to a data though state in response to the high level of the clock signal CLK and set to a data holding state in response to the low level of the clock signal CLK to load the new value held in the master latch circuit
22
of the data holding state in each data though state and to hold the new value as a preceding value in the data holding state set just after the data through state.
24
indicates an output driver for inverting and outputting the preceding value held in the slave latch circuit
23
.
The clock input driver
21
has both a first inverter and a second inverter. The first inverter is composed of a p-channel metal oxide semiconductor (PMOS) transistor
21
a
and an n-channel metal oxide semiconductor (NMOS) transistor
21
b
connected to each other at a drain connection terminal. The second inverter is composed of PMOS transistor
21
c
and an NMOS transistor
21
d
connected to each other at a drain connection terminal. The inverted phase clock signal TC is output from the drain connection terminal of the first inverter, and the positive phase clock signal T is output from the drain connection terminal of the second inverter.
The master latch circuit
22
has a switching element
22
a
, a switching element
22
b
, a third inverter composed of a PMOS transistor
22
c
and an NMOS transistor
22
d
and a fourth inverter composed of a PMOS transistor
22
e
and an NMOS transistor
22
f
. The switching element
22
a
and the third and fourth inverters are serially connected to each other in that order, and the switching element
22
b
is connected in parallel to the third and fourth inverters. A data signal D is input to the switching element
22
a
, and the value of the data signal D held in the master latch circuit
22
is output from a drain connection terminal of the fourth inverter.
The slave latch circuit
23
has a switching element
23
a
, a switching element
23
b
, a fifth inverter composed of a PMOS transistor
23
c
and an NMOS transistor
23
d
and a sixth inverter composed of a PMOS transistor
23
e
and an NMOS transistor
23
f
. The switching element
23
a
and the fifth and sixth inverters are serially connected to each other in that order, and the switching element
23
b
is connected in parallel to the fifth and sixth inverters. The value held in the master latch circuit
22
is input to the switching element
23
a
, an inverted output signal QC having a phase opposite to that of the data signal D is output from a drain connection terminal of the fifth inverter, and a positive output signal Q having the same phase as that of the data signal D is output from a drain connection terminal of the sixth inverter.
The output driver
24
has both a seventh inverter composed of a PMOS transistor
24
a
and an NMOS transistor
24
b
and an eighth inverter composed of a PMOS transistor
24
c
and an NMOS transistor
24
d
. The seventh and eighth inverters are connected in parallel to each other. The inverted output signal QC of the slave latch circuit
23
is input to the seventh inverter, and a positive phase output data signal Qout having the same phase as that of the data signal D is output from a drain connection terminal of the seventh inverter. Also, the positive output signal Q of the slave latch circuit
23
is input to the eighth inverter, and an inverted phase output data signal QCout having a phase opposite to that of the data signal D is output from a drain connection terminal of the eighth inverter.
Each of the switching elements
22
a
,
22
b
,
23
a
and
23
b
is composed of a PMOS transistor and an NMOS transistor, and an on state and an off state are alternately set in the switching element in response to the level changes of both the positive phase clock signal T and the inverted phase clock signal TC. The timing of the on and off states in the switching element
22
a
is the same as that in the switching element
23
b
, and the timing of the on and off states in the switching element
22
b
is the same as that in the switching element
23
a
. The on and off states of each switching element are set in correspondence to the high and low levels of the clock signal CLK.
For example, when the clock signal CLK set to the high level is changed to the low level, the positive phase clock signal T is set to the low level, and the inverted phase clock signal TC is set to the high level. Each of the switching elements
22
a
and
23
b
is set to the on state according to the clock signals T and TC, and each of the switching elements
22
b
and
23
a
is set to the off state according to the clock signals T and TC. In this case, the master latch circuit
22
is set to the data through state, and the data signal D passes through the switching element
22
a
and is input to the third and fourth inverters composed of the PMOS transistors
22
c
and
22
e
and the NMOS transistors
22
d
and
22
f
. Therefore, a new value of the data signal D is loaded in the master latch circuit
22
. At this time, in the slave latch circuit
23
, the switching circuit
23
a
is set to the off state, and the switching circuit
23
b
is set to the on state. Therefore, the slave latch circuit
23
is set to the data holding state so as to hold a preceding value which is received in the data through state just before the data holding state. The preceding value is output to the output driver
24
as the positive output signal Q, and an inverted value of the preceding value is output to the output driver
24
as the inverted output signal QC.
In contrast, when the clock signal CLK is set to the high level, the positive phase clock signal T is set to the high level, and the inverted phase clock signal TC is set to the low level. Each of the switching elements
22
a
and
23
b
is set to the off state according to the clock signals T and TC, and each of the switching elements
22
b
and
23
a
is set to the on state according to the clock signals T and TC. In this case, the master latch circuit
22
is set to the data holding state so as to hold the new value which is received in the data through state set just before the data holding state, and the slave latch circuit
23
is set to the data through state to receive the new value held in the master latch circuit
22
.
Therefore, the data through state and the data holding state are alternately set in the master latch circuit
22
in response to the clock signal CLK, the data holding state and the data through state different from the state of the master latch circuit
22
are alternately set in the slave latch circuit
23
in response to the clock signal CLK, and the positive phase output data signal Qout and the inverted phase data signal Qcout are output from the output driver
24
.
However, because the conventional master slave flip-flop circuit has the above-described configuration, twelve transistors composed of the PMOS transistor
21
a
, the NMOS transistor
21
b
, the PMOS transistor
21
c
, the NMOS transistor
21
d
, the four PMOS transistors of the switching elements
22
a
,
22
b
,
23
a
and
23
b
and the four NMOS transistors of the switching elements
22
a
,
22
b
,
Burns Doane Swecker & Mathis L.L.P.
Lam Tuan T.
Nguyen Hiep
Renesas Technology Corp.
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