Master-slave flip-flop circuit

Details Master-slave flip-flop circuit Master-slave flip-flop circuit

1999-12-08

2001-07-31

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S204000, C327S215000, C327S117000

Reexamination Certificate

active

06268752

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a master-slave flip-flop (F/F) circuit. More particularly, this invention relates to a master-slave flip-flop circuit having ECL (emitter coupled-logic) to be used as a frequency-dividing circuit or the like.
BACKGROUND OF THE INVENTION
FIG. 4
shows a conventional master-slave type flip-flop circuit. This master-slave type flip-flop circuit is structured by a master flip-flop MF′ and a slave flip-flop SF′Transistors used in this circuit are of npn-type.
The master flip-flop MF′ is structured by a differential circuit
101
for taking in input signals D and DB, a differential circuit
102
as an input stage of clocks T and TB (TB may be a reference voltage at which a high potential H level and a low potential L level of a T signal can be detected) connected in cascade to the differential circuit
101
, and a potential-setting circuit RL
101
for determining levels of data lines L
101
and L
102
.
The differential circuit
101
has transistors Q
101
and Q
102
having collectors connected in common, and transistors Q
103
and Q
104
having collectors connected in common. These transistors Q
101
, Q
102
, Q
103
and Q
104
constitute an ECL for collectors of transistors Q
105
and Q
106
of the differential circuit
102
. The input signals D and DB are applied to the bases of the transistors Q
101
and Q
104
respectively. The base of the transistor Q
102
is connected to a collector common connection line of the transistors Q
103
and Q
104
, and the base of the transistor Q
103
is connected to a collector common connection line of the transistors Q
101
and Q
102
.
The transistors Q
105
and Q
106
of the differential circuit
102
constitute an ECL for the collector of the transistor Q
113
, with clocks T and TB supplied to respective bases of these transistors Q
105
and Q
106
. The transistor Q
113
has an emitter grounded through an emitter resistor RE, and is constantly kept in an ON state due to a voltage VCB applied to the base.
The slave flip-flop SF′ is structured by a differential circuit
103
for taking in signals obtained from the data lines L
101
and L
102
, a differential circuit
104
as an input stage of clocks T and TB connected in cascade to the differential circuit
103
, and a potential-setting circuit RL
102
for determining levels of output signals Q and QB.
The differential circuit
103
has transistors Q
107
and Q
108
having collectors connected in common, and transistors Q
109
and Q
110
having collectors connected in common. These transistors Q
107
, Q
108
, Q
109
and Q
110
constitute an ECL for collectors of transistors Q
11
and Q
112
of the differential circuit
104
.
The transistor Q
107
has its base connected to the collector common connection line of the transistors Q
101
and Q
102
by the data line L
101
. The transistor Q
110
has its base connected to the collector common connection line of the transistors Q
103
and Q
104
by the data line L
102
. The transistor Q
108
has its base connected to a collector common connection line of the transistors Q
109
and Q
110
. Similarly, the transistor Q
109
has its base connected to a collector common connection line of the transistors Q
107
and Q
108
. An output signal Q is taken out from the collector common connection line of the transistors Q
107
and Q
108
. Similarly, an output signal QB is taken out from the collector common connection line of the transistors Q
109
and Q
110
.
The transistors Q
111
and Q
112
of the differential circuit
104
constitute an ECL for the collector of a transistor Q
114
, with clocks T and TB supplied to respective bases of these transistors Q
111
and Q
112
. The transistor Q
114
has an emitter grounded through an emitter resistor RE, and is constantly kept in an ON state due to a voltage VCB applied to the base.
According to the master-slave type flip-flop circuit having the ECL structure as described above, as shown in
FIG. 5
, an output signal terminal (QB) and an input signal terminal (D) are short-circuited, and an output signal terminal (Q) and an input signal terminal (DB) are short-circuited. Therefore, the master-slave type flip-flop circuit operates as a frequency-dividing circuit.
Next, the operation of the frequency-dividing circuit formed by the line connection shown in
FIG. 5
will be explained in four stages with reference to an input and output waveform diagram shown in FIG.
6
.
At first, (
1
) in
FIG. 6
is assumed as a first stage. When a clock T has changed from a high potential H to a low potential L, and when a clock TB has changed from a low potential L to a high potential H, the transistor Q
105
of the differential circuit
102
changes from OFF to ON, the transistor Q
106
changes from ON to OFF, the transistor Q
111
of the differential circuit
104
changes from OFF to ON, and the transistor Q
112
changes from ON to OFF.
Along with the change in the state of the differential circuit
102
, the transistor Q
101
of the differential circuit
101
changes from ON to OFF, the transistor Q
102
changes from OFF to ON, the transistors Q
103
and Q
104
keep OFF state, the data line L
101
keeps a low potential L, and the data line L
102
keeps a high potential H, and data is held in this state.
Further, along with the change in the state of the differential circuit
104
, the transistor Q
107
of the differential circuit
103
keeps an OFF status, the transistor Q
108
changes from ON to OFF, the transistor Q
109
keeps OFF state, the transistor Q
110
changes from OFF to ON, the output Q changes from a low potential L to a high potential H, and the output QB changes from a high potential H to a low potential L. Along with the changes in the status of the outputs Q and QB, the base potential of the transistor Q
101
changes from a high potential H to a low potential L, and the base potential of the transistor Q
104
changes from a low potential L to a high potential H.
Next, (
2
) in
FIG. 6
is assumed as a second stage. When the clock T has changed from the low potential L to a high potential H, and when the clock TB has changed from the high potential H to a low potential L, the transistor Q
105
of the differential circuit
102
changes from ON to OFF, the transistor Q
106
changes from OFF to ON, the transistor Q
11
of the differential circuit
104
changes from ON to OFF, and the transistor Q
112
changes from OFF to ON.
Along with the change in the status of the differential circuit
102
, the transistor Q
101
of the differential circuit
101
keeps OFF state, the transistor Q
102
changes from ON to OFF, the transistor Q
103
keeps OFF state, and the transistor Q
104
changes from OFF to ON, the data line L
101
changes from the low potential L to a high potential H, and the data line L
102
changes from a high potential H to a low potential L.
Further, along with the change in the state of the differential circuit
104
, the transistors Q
107
and Q
108
of the differential circuit
103
keep OFF state, the transistor Q
109
changes from OFF to ON, the transistor Q
110
changes from ON to OFF, the output Q keeps the high potential H, and the output QB keeps the low potential L. Along with the changes in the state of the data lines L
101
and L
102
, the base potential of the transistor Q
107
changes to a low potential L, and the base potential of the transistor Q
110
changes to a high potential H.
Next, (
3
) in
FIG. 6
is assumed as a third stage. When the clock T has changed from the high potential H to a low potential L, and when the clock TB has changed from the low potential L to a high potential H, the transistor Q
105
of the differential circuit
102
changes from OFF to ON, the transistor Q
106
changes from ON to OFF, the transistor Q
11
of the differential circuit
104
changes from OFF to ON, and the transistor Q
112
changes from ON to OFF.
Along with the change in the status of the differential circuit
102
, the transistors Q
101
and Q
102
of the differential circuit
101
keep OFF state, the transistor Q
103
c

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