Master-slave flip-flop circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

Patent

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Details

307247R, 307289, 324 73R, 328 48, 328195, 328196, 365201, H03K 3286, H03K 1700, H03K 2132, G01R 1512

Patent

active

041568192

ABSTRACT:
A logic circuit, which includes master-slave flip-flops, advantageously designed to place both the master and the slave flip-flops in a predetermined logic state so that the logic circuit can be tested in one clock cycle in the same manner as a combinational logic circuit is tested.

REFERENCES:
patent: 3336579 (1967-08-01), Heymann
patent: 3440449 (1969-04-01), Priel et al.
patent: 3454935 (1969-07-01), Hippisley, Jr.
patent: 3609569 (1971-09-01), Todd
patent: 3617776 (1971-11-01), Priel
patent: 3673397 (1972-06-01), Schaefer
patent: 3728561 (1973-04-01), Brocker, Jr.
patent: 3814953 (1974-06-01), Malaviya
patent: 3873818 (1975-03-01), Barnard
patent: 3878405 (1975-04-01), Sylvan
patent: 3917961 (1975-11-01), Reed

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