Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-12-29
2001-06-05
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S201000
Reexamination Certificate
active
06242958
ABSTRACT:
FIELD OF THE INVENTION
Embodiments of the present invention provide a flip-flop circuit. In particular, the present invention provides a master-slave flip-flop having a dynamic master and a static slave.
BACKGROUND OF THE INVENTION
Important characteristics of an integrated circuit are the amount of power it consumes, the amount of area it takes up, and the speed of the circuit. In most cases, it is advantageous for a circuit to minimize power consumption and area and to maximize speed. One approach used to save power in an integrated circuit is temporarily stopping the clock in part of the circuit that is not operating. A clock is stopped when it remains in a state (e.g., active or inactive) for an extended period of time. A clock may be considered to be in the active state when it is at a high voltage. Typically, only ten percent of an integrated circuit is operating at any one time, and it is advantageous to stop the clock to the other ninety percent of the circuit if possible. Temporarily stopping the clock to a part of the circuit reduces power consumption, without degrading the accuracy of the integrated circuit, because circuit elements will not use as much power when the clock for that part of the circuit is stopped.
Flip-flops are basic building blocks of sequential logic circuits, and modern microprocessors contain thousands of flip-flops. A flip-flop typically comprises a master component, which latches data input when the clock is in a first state, and a slave component, which latches data from the master when the clock is in a second state.
FIG. 1
shows a prior flip-flop
100
which has a master latch
101
and a slave latch
102
. Clock
121
cycles between an active (high) state and an inactive (low) state. Master
101
is a static latch because it holds data for an indefinite period of time after clock
121
is stopped. In particular, master latch
101
has a keeper
110
that maintains its state when the clock
121
is stopped. Persons of ordinary skill in the art will appreciate that keeper
110
maintains its state, regardless of any change in the state of clock
121
, until new data is input through data line
130
. Slave latch
102
is also a static latch and has a keeper
120
.
One concern with stopping the clock in an integrated circuit is that the circuit could lose data, which would generally be unacceptable. For example, if master latch
101
of flip-flop
100
where to change its state when clock
121
is stopped in the active state, this new state (i.e., new data) would be imparted to slave latch
102
, which takes on the state of the master latch when the clock is in the active state. For this reason, prior art systems that allow the clock to stop use static latches to prevent the state of the latches from drifting during the time that the clock is stopped. Master latch
101
will not change its state until the clock
121
becomes inactive because keeper
101
maintains its state indefinitely when clock
121
is stopped in the active state. Thus, the data in master latch
101
will not be lost. However, the inclusion of keeper
110
and keeper
120
in prior art flip-flop
100
increases the area and power consumption of the flip-flop and decreases the speed of the circuit. The removal of keeper
110
, for example, results in an approximately ten percent decrease in the power consumed, ten percent reduction in area, and ten percent reduction in the circuit delay. This savings is significant because modem microprocessors contain such a large number of flip-flops.
Based on the foregoing, there is a need for a flip-flop which has a reduced number of gates but which allows the clock to be stopped without data loss.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide a flip-flop circuit. The flip-flop circuit comprises a dynamic master coupled to a clock, and a static slave coupled to the clock and coupled to the dynamic master. The clock is characterized by a first state of a maximum duration.
REFERENCES:
patent: 4469962 (1984-09-01), Snyder
patent: 5784384 (1998-07-01), Maeno
patent: 6097230 (2000-08-01), Bareither
Intel Corporation
Kenyon & Kenyon
Tran Toan
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