Master-slave flip-flop and method

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

Reexamination Certificate

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Reexamination Certificate

active

06188260

ABSTRACT:

TECHNICAL FIELD
The present invention is generally related to the field of integrated logical circuits and, more particularly, is related to a master-slave flip-flop and associated method.
BACKGROUND OF THE INVENTION
Currently, logical circuits are employed in a nearly infinite number of applications, such as microprocessors and other integrated circuits. In the case of microprocessors, for example, these logical circuits are designed to operate at ever increasing speeds to facilitate the execution of larger and more complex software packages.
The logical circuits may be designed using a multitude of components to accomplish a specific purpose as part of a microprocessor circuit or other integrated circuit. These components may include various logical gates, registers, inverters, amplifiers, or other devices which are created using transistors such as junction field-effect transistors (JFET's) and metal-oxide semiconductor field-effect transistors (MOSFET's) and other circuit elements.
One such logical circuit is called a “master-slave flip-flop” which is often used to capture a specific logical value in a microprocessor or other complex circuit. For example, master-slave flip-flops may be used to capture and store a logical value to be applied to critical path circuits which drive output pads, for example, in a microprocessor or other integrated circuit. The capture of the logical value may be performed according to a clock pulse or other activation signal input.
SUMMARY OF THE INVENTION
The present invention provides a master-slave flip-flop and method for use with critical path circuits, for example, but not limited to, driving output pads on an integrated circuit. Briefly described, in architecture, the master-slave flip-flop comprises a master stage and a slave stage. The master stage includes a pass gate, an input inverter coupled to the pass gate, a feedback inverter coupled across the input inverter, and a driving inverter coupled to the output of the input inverter. The output of the driving inverter is coupled to the slave stage which includes a second pass gate through which the output of the driving inverter is applied to the master-slave flip-flop output.
The present invention can also be viewed as providing a method for maintaining a logical value in a master-slave flip-flop. In this regard, the method can be broadly summarized by the following steps: applying a logical voltage value to an input inverter; maintaining the logical voltage value in the input inverter using a feedback inverter; driving the logical voltage value from the input inverter to a slave stage using a driving inverter; applying the output of the driving inverter to a bus; and, maintaining the logical voltage value on the bus.
The present invention has numerous advantages, a few of which are delineated hereafter. For example, the master-slave flip-flop includes a fast setup time and a fast clock-to-output time (also termed clock-to-Q herein) without the problems associated with charge sharing which may cause loss of state in the master stage due to high capacitance on the output node (also termed kickback herein). Also, the output of the master-slave flip-flop is tristatable. Further, the master-slave flip-flop according to the invention is simple in design, user friendly, robust and reliable in operation, efficient in operation, and easily implemented for mass commercial production.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention.


REFERENCES:
patent: 3539836 (1970-11-01), Seelbach et al.
patent: 3984702 (1976-10-01), Fett
patent: 4258273 (1981-03-01), Straznicky et al.
patent: 4419762 (1983-12-01), Paul
patent: 4495629 (1985-01-01), Zasio et al.
patent: 5107137 (1992-04-01), Kinugasa et al.
patent: 5264738 (1993-11-01), Veendrick et al.

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