Master-slave flip-flop and clocking scheme

Details Master-slave flip-flop and clocking scheme Master-slave flip-flop and clocking scheme

2007-03-08

2008-08-05

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S218000

Reexamination Certificate

active

07408393

ABSTRACT:
A master-slave flip-flop comprises master and slave latches, with the data output of the master latch connected to the data input of the slave latch. The latches receive clock signals CKM and CKS at their respective clock inputs; each latch is transparent when its clock signal is in a first state and latches a signal applied to its input when its clock signal is in a second state. A clock buffer receives an input clock CKinand generates nominally complementary clock signals CKM and CKS such that one latch is latched while the other is transparent. The clock buffer is arranged to skew CKS with respect to CKM such that the slave latch is made transparent earlier than it would without the skew, making the minimum delay (tpd) between the toggling of CKinand a resulting change at the slave latch's output less than it would otherwise be.

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Jedec Standard; “Definition of the SSTUB32866 1.8-V Configurable Registered Buffer With Parity Test for DDR2 RDIMM Applications”; Jedec Solid State Technology Association; Jan. 2006; pp. 1-36.

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