Master-slave D-type flip-flops with improved voltage offset mean

Details Master-slave D-type flip-flops with improved voltage offset mean Master-slave D-type flip-flops with improved voltage offset mean

1988-01-21

1989-04-25

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307491, 3072992, H03K 3289

Patent

active

048250970

ABSTRACT:
A master-slave D-type flip-flop includes a master section (14) and a slave section (16). The master section (14) has a master clock differential transistor pair formed of a first input transistor (MQ14) and a first reference transistor (MQ13) whose emitters are connected together. The slave section (16) has a slave clock differential transistor pair formed of a second input transistor (SQ9) and a second reference transistor (SQ10) whose emitters are connected together. An improved voltage offset means is provided for creating a separation of thresholds between the master section and the slave section. The offset voltage means is formed of the first input transistor (MQ14) of the master section having dual-emitters and of the second reference transistor (SQ10) of the slave section having dual-emitters.

REFERENCES:
patent: 4289979 (1981-09-01), Muller
patent: 4359647 (1982-11-01), Trinkl

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