Master-slave clocked flip-flop circuit

Details Master-slave clocked flip-flop circuit Master-slave clocked flip-flop circuit

1991-03-12

1992-12-08

Howell, Janice A.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307289, 307291, 3072722, 377 74, 377 78, 377 79, H03K 329, H03K 3289

Patent

active

051700743

ABSTRACT:
A flip-flop of a master-slave type of a CMOS structure having no P channel transistor between nodes of the master flip-flop and of the slave flip-flop is provided. Only one P channel MOS transistor is existent in a route of the current controlling a rise time and a trail time of output signals, so that it is possible to function at a high speed.

REFERENCES:
patent: 4703200 (1987-10-01), Zangara
"Two phase MOSFET static shift register employee feedback stage resetting" Fisher, IBM Tech. Disc. Bul. vol. 15 No. 6 Nov. 1972.

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