Master-slave clocked CMOS flip-flop with hysteresis

Details Master-slave clocked CMOS flip-flop with hysteresis Master-slave clocked CMOS flip-flop with hysteresis

1990-09-04

1992-04-21

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307481, 307290, H03K 513, H03K 1900

Patent

active

051071371

ABSTRACT:
In a master-slave type flip-flop circuit comprising a master output holding circuit of the master stage circuit, the threshold value of the input circuit of the slave stage circuit has a hysteresis characteristic in which the high level threshold value is set to a higher value than the threshold value of the master output holding circuit and the low level threshold value is set to a lower value than the threshold value of the master output holding circuit. Due to the feature, a phenomenon is prevented in which the output is once inverted and then again inverted in the metastable state.

REFERENCES:
patent: 4495628 (1985-01-01), Zasio
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4554467 (1985-11-01), Vaughn
patent: 4820939 (1989-04-01), Sowell et al.
patent: 4843254 (1989-06-01), Motegi et al.
patent: 5015875 (1991-05-01), Giles et al.

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