Master-slave cache system for instruction and data cache memorie

Details Master-slave cache system for instruction and data cache memorie Master-slave cache system for instruction and data cache memorie

1994-06-29

1996-08-27

Swann, Tod R.

395450, 395455, 395457, 395459, 395460, 395462, 395463, 395467, 395471, 395473, 395469, G06F 1208

Patent

active

055510019

ABSTRACT:
A master-slave cache system has a large, set-associative master cache, and two smaller direct-mapped slave caches, a slave instruction cache for supplying instructions to an instruction pipeline of a processor, and a slave data cache for supplying data operands to an execution pipeline of the processor. The master cache and the slave caches are tightly coupled to each other. This tight coupling allows the master cache to perform most cache management operations for the slave caches, freeing the slave caches to supply a high bandwidth of instructions and operands to the processor's pipelines. The master cache contains tags that include valid bits for each slave, allowing the master cache to determine if a line is present and valid in either of the slave caches without interrupting the slave caches. The master cache performs all search operations required by external snooping, cache invalidation, cache data zeroing instructions, and store-to-instruction-stream detection. The master cache interrupts the slave caches only when the search reveals that a line is valid in a slave cache, the master cache causing the slave cache to invalidate the line. A store queue is shared between the master cache and the slave data cache. Store data is written from the store queue directly in to both the slave data cache and the master cache, eliminating the need for the slave data cache to write data through to the master cache. The master-slave cache system also eliminates the need for a second set of address tags for snooping and coherency operations. The master cache can be large and designed for a low miss rate, while the slave caches are designed for the high speed required by the processor's pipelines.

REFERENCES:
patent: 4467414 (1984-08-01), Akagi et al.
patent: 4707784 (1987-11-01), Ryan et al.
patent: 5019971 (1991-05-01), Lefsky et al.
patent: 5023776 (1991-06-01), Gregor
patent: 5136700 (1992-08-01), Thacker
patent: 5155824 (1992-10-01), Edenfield et al.
patent: 5155828 (1992-10-01), Le Fetra et al.
patent: 5155831 (1992-10-01), Emma et al.
patent: 5170476 (1992-12-01), Laakso et al.
patent: 5179679 (1993-01-01), Shoemaker
patent: 5201041 (1993-04-01), Bohner et al.
patent: 5202969 (1993-04-01), Sato et al.
patent: 5212781 (1993-05-01), Shah
patent: 5249282 (1993-09-01), Segers
patent: 5276848 (1994-01-01), Gallagher et al.
patent: 5283890 (1994-02-01), Petolino et al.
Blasco et al., "Inspection Cache Buffer With Program-Flow Control". Originally Published As U.S. Pat. No. 5,131,088.

Affiliated with

Also associated with

Rating

Master-slave cache system for instruction and data cache memorie does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Master-slave cache system for instruction and data cache memorie, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Master-slave cache system for instruction and data cache memorie will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1063225