Master-slave bistable latch with clock input control

Details Master-slave bistable latch with clock input control Master-slave bistable latch with clock input control

1996-02-28

1997-12-30

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327215, H03K 3289

Patent

active

057035130

ABSTRACT:
It is an object to obtain a semiconductor integrated circuit with reduced power consumption without reducing operation speed. In clock input control means (27), an exclusive OR gate (26a) receives comparison data (S1 and S2) and an NAND gate (27a) receives output of the exclusive OR gate (26a) and a reference clock (T) and outputs its output, a control signal (SC1) to an AND gate (G1) and an AND gate (G2) in a data holding portion (31a). An exclusive OR gate (26b) receives comparison data (S3 and S4) and an NAND gate (27b) receives the output of the exclusive OR gate (26b) and the reference clock (T), and outputs its output, a control signal (SC2) to an OR gate (G5) and an OR gate (G6) in a data holding portion (31b). Appropriately selecting the comparison data (S1-S4) allows data transfer at high speed of input data (D), output data (Q), inverted output data (QC), and so forth.

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