1995-05-08
1997-11-25
Ray, Gopal C.
395308, 395872, 395250, G06F 1300, G06F 1338, G06F 1340
Patent
active
056921373
ABSTRACT:
An interface between two buses in different clock domains. The interface includes a master buffer which is used for both master writes and slave reads. A control logic unit for each bus receives signals from a buffer manager which straddles the clock domains to gate latch pulses to the master buffer.
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Flaig Charles M.
Regal Michael L.
Apple Computer Inc.
Ray Gopal C.
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