Master oriented bus bridge

Details Master oriented bus bridge Master oriented bus bridge

1995-05-08

1997-11-25

Ray, Gopal C.

395308, 395872, 395250, G06F 1300, G06F 1338, G06F 1340

Patent

active

056921373

ABSTRACT:
An interface between two buses in different clock domains. The interface includes a master buffer which is used for both master writes and slave reads. A control logic unit for each bus receives signals from a buffer manager which straddles the clock domains to gate latch pulses to the master buffer.

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patent: 5615382 (1997-03-01), Gavin et al.
IBM Corp., "Synchronization And Speed-Tracking Logic for Slave-Driven Transfers", Sep. 1990, vol. 33, No. 4, pp. 423-432.

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