Master clock input circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression

Reexamination Certificate

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Details

C327S291000, C331S1160FE

Reexamination Certificate

active

06853240

ABSTRACT:
A master clock input circuit with excellent amplification characteristics which generates little noise during mode switching. In a master clock input circuit, the output electric potential of an amplification gate circuit (for example, a NOR gate) is superimposed on a master clock and supplied to the input terminal of an amplification gate circuit. A transmission gate circuit and impedance control gate are provided between the output terminal and input terminal. The transmission gate circuit has low impedance and the impedance control circuit has high impedance. The transmission gate circuit opens and closes the line between the output terminal and input terminal of the amplification gate circuit. Since the impedance of the transmission gate circuit is low, generation of noise is reduced. In addition, since the impedance of the impedance control circuit is high, the amplification factor of the amplification gate circuit becomes higher.

REFERENCES:
patent: 5905682 (1999-05-01), Gans et al.
patent: 6150862 (2000-11-01), Vikinski
patent: 6177847 (2001-01-01), Nagasue
patent: 6326823 (2001-12-01), Okui
patent: 6600353 (2003-07-01), Linam et al.
patent: 64-080105 (1989-03-01), None
patent: 05-335913 (1993-12-01), None
patent: 06120805 (1994-04-01), None
patent: 08-079042 (1996-03-01), None
patent: 2001-51744 (2001-02-01), None

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