Massively parallel supercomputer

Details Massively parallel supercomputer Massively parallel supercomputer

2002-02-25

2009-06-30

Etienne, Ario (Department: 2457)

Electrical computers and digital processing systems: multicomput

Multiple network interconnecting

C709S200000, C709S220000, C712S001000, C712S010000

Reexamination Certificate

active

07555566

ABSTRACT:
A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node may be used individually or simultaneously to work on any combination of computation or communication as required by the particular algorithm being solved or executed at any point in time. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. In the preferred embodiment, the multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. For particular classes of parallel algorithms, or parts of parallel calculations, this architecture exhibits exceptional computational performance, and may be enabled to perform calculations for new classes of parallel algorithms. Additional networks are provided for external connectivity and used for Input/Output, System Management and Configuration, and Debug and Monitoring functions. Special node packaging techniques implementing midplane and other hardware devices facilitates partitioning of the supercomputer in multiple networks for optimizing supercomputing resources.

REFERENCES:
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Lakshmivarahan, et al., “Ring, torus and 1-9 hypercube architectures/algorithms for parallel computing”, Parallel Computing, Elsevier Publishers, Amsterdam, NL, vol. 25, No. 13-14, Dec. 1, 1999, pp. 1877-1906, XP004363665, ISSN: 0167-8191.

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