Massively parallel array processor

Details Massively parallel array processor Massively parallel array processor

1995-03-23

2002-06-11

Davis, George B. (Department: 2122)

Data processing: artificial intelligence

Neural network

Structure

C706S014000, C706S042000, C712S019000

Reexamination Certificate

active

06405185

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to computers and particularly to parallel array processors.
CROSS REFERENCE TO RELATED APPLICATIONS
The present U.S. patent application claims priority as a continuation-in-part application and is related to the following applications:
U.S. Ser. No. 07/526,866 filed May 22, 1990, of S. Vassiliadis et al, entitled: Orthogonal Row-Column Neural Processor (now U.S. Pat. No. 5,065,339, issued Nov. 12, 1991); and
U.S. Ser. No. 07/740,355 filed Aug. 5, 1991, of S. Vassiliadis et al, entitled: Scalable Nerual Array Processor, issued as U.S. Pat. No. 5,146,543; and,
U.S. Ser. No. 07/740,556 filed Aug. 5, 1991, of S. Vassiliadis et al, entitled: Adder Tree for a Neural Array Processor, issued as U.S. Pat. No. 5,146,420 and,
U.S. Ser. No. 07/740,568 filed Aug. 5, 1991, of S. Vassiliadis et al, entitled: Apparatus and Method for Neural Processor, abandoned in favor of U.S. Ser. No. 08/000,915, filed Jan. 6, 1993, issued as U.S. Pat. No. 5,251,287 and,
U.S. Ser. No. 07/740,266 filed Aug. 5, 1991, of S. Vassiliadis et al, entitled: Scalable Neural Array Processor and Method, issued as U.S. Pat. No. 5,148,515 and
U.S. Ser. No. 07/682,786 filed Apr. 8, 1991, of G. G. Pechanek et al, entitled: Triangular Scalable Neural Array Processor, abandoned in favor of continuation application U.S. Ser. NO. 08/231,853, filed Apr. 22, 1994, (now co-pending).
These applications and the present continuation-in-part application are owned by one and the same assignee, namely, International Business Machines Corporation of Armonk, N.Y.
The descriptions set forth in these above applications are hereby incorporated into the present application.
GLOSSARY OF TERMS
ALU
ALU is the arithmetic logic unit portion of a processor.
Array
Array refers to an arrangement of elements in one or more dimensions.
Array processors are computers which have many functional units or PEs arranged and interconnected to process in an array. Massively parallel machines use array processors for parallel processing of data arrays by array processing elements or array elements. An array can include an ordered set of data items (array element) which in languages like Fortran are identified by a single name, and in other languages such a name of an ordered set of data items refers to an ordered collection or set of data elements, all of which have identical attributes. An program array has dimensions specified, generally by a number or dimension attribute. The declarator of the array may also specify the size of each dimension of the array in some languages. In some languages, an array is an arrangement of elements in a table. In a hardware sense, an array is a collection of structures (functional elements) which are generally identical in a massively parallel architecture. Array elements in data parallel computing are elements which can be assigned operations, and when parallel can each independently and in parallel execute the operations required. Generally arrays may be thought of as grids of processing elements. Sections of the array may be assigned sectional data, so that sectional data can be moved around in a regular grid pattern. However, data can be indexed or assigned to an arbitrary location in an array.
Functional unit
A functional unit is an entity of hardware, software, or both, capable of accomplishing a purpose.
MIMD
A processor array architecture wherein each processor in the array has its own instruction stream, thus Multiple Instruction stream, to execute Multiple Data streams located one per processing element.
Module
A module is a program unit that is discrete and identifiable, or a functional unit of hardware designed for use with other components.
PE
PE is used for processing element. We use the term PE to refer to a single processor, which has interconnected allocated memory and I/O capable system element or unit that forms one of our parallel array processing elements. As the result of wiring, in our system, symmetric replicatable elements, are wired together for sharing interconnection paths.
SIMD
A processor array architecture wherein all processors in the array are commanded from a Single Instruction stream, to execute Multiple Data streams located one per processing element.
REFERENCES USED IN THE DISCUSSION OF THE INVENTION
During the detailed description which follows the following works will be referenced as an aid for the reader. These additional references are:
1. R. J. Gove, W. Lee, Y. Kim, and T. Alexander, “Image Computing Requirements for the 1990s: from Multimedia to Medicine,”
Proceedings of the SPIE Vol.
1444
—Image Capture, Formatting, and Display
, pp. 318-333, 1991.
2. R. Cypher and J. L. C. Sanz, “SIMD Architectures and Algorithms for Image Processing and Computer Vision,”
IEEE Transactions on Acoustics, Speech, and Signal Processing
, Vol. 37, No. 12, pp. 2158-2174, December 1989.
3. K. E. Batcher, “Design of a Massively Parallel Processor,”
IEEE Transactions on Computers
Vol. C-29, No. 9, pp. 836-840, September 1980.
4. L. Uhr,
Multi-Computer Architectures for Artificial Intelligence
, New York, N.Y.: John Wiley & Sons, chap. 8, p.97, 1987.
5. S.-Y. Lee and J. K. Aggarwal, “Parallel 2-D Convolution on a Mesh Connected Array Processor,”
IEEE Transactions on Pattern Analysis and Machine Intelligence
, Vol. PAMI-9, No. 4, pp. 590-594, July 1987.
6. E. B. Eichelberger and T. W. Williams, “A Logic Design Structure for Testability,”
Proc.
14
th Design Automation Conference
, IEEE, 1977.
7. D. M. Young and D. R. Kincaid, “A Tutorial on Finite Difference Methods and Ordering of Mesh Points,”
Proceedings of the Fall Joint Computer Conference
, pp. 556-559, Dallas, Tex.: IEEE Press, November 1986.
8. E. Kreyszig,
Advanced Engineering Mathematics
. New York, N.Y.: John Wiley & Sons, chap. 9.7, pp. 510-512, 1968.
9. U.S. Ser. No. 07/799,602, filed Nov. 27, 1991, by H. Olnowich, entitled: “Multi-Media Serial Line Switching Adapter for Parallel Networks and Heterogenous and Homologous Computer Systems”. systems which allow dynamic switching between MIMD, SIMD, and SISD.
10. U.S. Ser. No. 07/798,788, filed Nov. 27, 1991, by P. M. Kogge, entitled: “Dynamic Multi-mode Parallel Processor Array Architecture”.
These additional references are incorporated by reference.
BACKGROUND OF THE INVENTION
As background for our invention, the processing of visual information can be considered to consist of three different processing domains: image processing, pattern recognition, and computer graphics. The merger of image processing, pattern recognition and computer graphics is referred to as image computing and represents a capability required by the multimedia workstations of the future. “Multimedia refers to a technique that presents information in more than one way, such as via images, graphics, video, audio, and text, in order to enhance the comprehensibility of the information and to improve human-computer interaction” (See Additional Reference 1).
In the never ending quest for faster computers, engineers are linking hundreds, and even thousands of low cost microprocessors together in parallel to create super supercomputers that divide in order to conquer complex problems that stump today's machines. Such machines are called massively parallel. Multiple computers operating in parallel have existed for decades.
Early parallel machines included the ILLIAC which was started in the 1960s. Other multiple processors include (see a partial summary in U.S. Pat. No. 4,975,834 issued Dec. 4, 1990 to Xu et al) the Cedar, Sigma-1, the Butterfly and the Monarch, the Intel ipsc, The Connection Machines, the Caltech COSMIC, the N Cube, IBM's RP3, IBM's GF11, the NYU Ultra Computer, the Intel Delta and Touchstone.
Large multiple processors beginning with ILLIAC have been considered supercomputers. Supercomputers with greatest commercial success have been based upon multiple vector processors, represented by the Cray Research Y-MP systems, the IBM 3090, and other manufacturer's machines including those of Amdahl, Hitachi, Fujitsu, and NEC.
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