Boots – shoes – and leggings
Patent
1995-11-13
1997-08-05
Geckil, Mehmet B.
Boots, shoes, and leggings
395381, 364DIG1, 364230, 364247, 364240, G06F 930
Patent
active
056551339
ABSTRACT:
A massively multiplexed central processing unit ("CPU") which has a plurality of independent computational circuits, a separate internal result bus for transmitting the resultant output from each of these computational circuits, and a plurality of general purpose registers coupled to each of the computational circuits. Each of the general purpose registers have multiplexed input ports which are connected to each of the result buses. Each of the general purpose registers also have an output port which is connected to a multiplexed input port of at least one of the computational circuits. Each of the computational circuits are dedicated to at least one unique mathematical function, and at least one of the computational circuits include at least one logical function. At least one of the computational circuits includes a plurality of concurrently operable mathematical and logical processing circuits, and an output multiplexer for selecting one of the resultant outputs for transmission on its result bus. The CPU also features a very long instruction word which uses a series of assigned bit locations to represent the selections codes for each of the CPU components. These selection codes are directly transmitted to each of the CPU components by a program control circuit. A separate data control circuit is further provided in achieve a Harvard architecture design for the CPU.
REFERENCES:
patent: 3905023 (1975-09-01), Perpiglia
patent: 4430708 (1984-02-01), Isaman
patent: 4493020 (1985-01-01), Kim et al.
patent: 4494187 (1985-01-01), Simpson
patent: 4506322 (1985-03-01), Leigh
patent: 4566595 (1986-01-01), Fustier
patent: 4587632 (1986-05-01), Ditzel
patent: 4608634 (1986-08-01), Caudel et al.
patent: 4608661 (1986-08-01), Sasaki
patent: 4747039 (1988-05-01), Murray
patent: 4748439 (1988-05-01), Robinson et al.
patent: 4751675 (1988-06-01), Knauer
patent: 4787062 (1988-11-01), Nei et al.
patent: 4791550 (1988-12-01), Stevenson et al.
patent: 4891787 (1990-01-01), Gifford
patent: 4918586 (1990-04-01), Niimura et al.
patent: 4964046 (1990-10-01), Mehrgandt et al.
patent: 4992934 (1991-02-01), Portanova et al.
patent: 5003462 (1991-03-01), Blaner et al.
patent: 5034887 (1991-07-01), Yasui et al.
patent: 5051940 (1991-09-01), Vassiliadis et al.
patent: 5081573 (1992-01-01), Hall et al.
patent: 5084836 (1992-01-01), Yamaguchi
patent: 5218564 (1993-06-01), Covey
patent: 5301340 (1994-04-01), Cook
patent: 5305446 (1994-04-01), Leach et al.
patent: 5313551 (1994-05-01), Labrousse et al.
patent: 5319789 (1994-06-01), Ehlig et al.
patent: 5329631 (1994-07-01), Ishibashi et al.
patent: 5442760 (1995-08-01), Rustad et al.
patent: 5513363 (1996-04-01), Kumar et al.
Colwell, Robert P. et al., "A VLIW Architecture for a Trace Scheduling Compiler," Proceedings Second International Conference on Architecture Support for Programming languages and Operating Systems, Oct. 5-8, 1987, Palo ALto, California, pp. 180-192.
Jouppi, Norman P. "Available Instruction-Level Parllelism for Superscalar and Superpipelined Machines" Architectural Support for Programming Languages and Operating Systems Proceedings, Apr. 3-6, 1989, 272-282.
Smith, Michael D. et al., "Limits on Multiple Instruction Issue," Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, Apr. 3-6, 1989, pp. 290-302.
"Proceedings: Advanced Computer Technology, Reliable Systems and Applications," 5th Annual European Computer Conference, May 13-16, 1991, IEEE Computer Society Press Order No. 2141, Library of Congress No. 91-070547, IEEE Catalog No. 91CH30001-5, pp. 368-372.
Nakajima et al., "OHMEGA: A VLSI Superscalar Processor Architecture for Numerical Applications," 8345 Computer Architecture News, 18th Annual Int. On Computer Architecture, 19(1991) May, No. 3, New York, pp. 160-168.
Edward McLelland, "The Alpha AXP Architecture and 21064 Processor," IEEE Micro, Jun. 1993, No. 3, Los Alamitos, CA, pp. 36-40.
Mini/Micro computer design--Kraft & Toy--Prentice Hall publications.
Microprogrammable Computer Architectures--Alan B. Salisbury--1976.
i860 Microprocessor Architecture--Neal Margulis--1990.
James W. Hess, "Alternative computer architecture reduce bottlenecks." EDN, Nov. 12, 1987 pp. 271-278.
Bleck James A.
Bressette William J.
Churchill Stephen G.
Dupree Wayne P.
Gallant Jeffry R.
Geckil Mehmet B.
The Dow Chemical Company
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