Massive parallel semiconductor manufacturing test process

Details Massive parallel semiconductor manufacturing test process Massive parallel semiconductor manufacturing test process

2000-06-08

2002-08-13

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C365S201000

Reexamination Certificate

active

06433568

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to temperature cycling units and integrated circuit testing systems and, more specifically, to a massive parallel semiconductor manufacturing test process.
BACKGROUND OF THE INVENTION
Integrated circuit (IC) testing is divided into two main stages: package level burn-in and device testing. The package level burn-in is a 24 hour, 125 degree Celsius (C) process which performs device exercising. The package level burn-in is often referred to as a “package level test-in-burn-in” (PLTIBI) and utilizes a burn-in oven and an integrated burn-in environment (IBE) system that can exercise a relatively large number of about 1,248 devices simultaneously. A thousand may also be considered a large number. Since the package level hardware does not contain any external analog-to-digital converters, digital-to-analog converters, etc., the package level burn-in stage cannot perform functional testing on the device.
The device test stage is utilized to test the functional components of the device. The device test stage includes three steps that test the device at 25 degrees C (Celsius), 140 degrees C, and minus or negative 40 degrees C. The device test stage can only test a relatively small number of devices or ICs at a time. This may be as small as one per machine, but 32 can also be considered a small number. For example, testing the flash in a microprocessor device is a very lengthy process. Since there are many flash tests in the test stage, the time period per device is lengthy and increases test time dramatically. In efforts to overcome the delay, the hot testing of flash has been moved to the package level burn-in stage of the IC testing. However, cold testing is still performed at the test stage of the package level testing and contributes to undesirable delays in the IC testing.
In the first stage of the IC testing, during the burn-in, portions of an integrated circuit such as flash memory are only exercised, i.e., data is written into the memory, and testing does not occur at the burn-in stage of the IC testing. It would be a significant advantage if flash memory could be tested in parallel at the burn-in stage of the IC testing instead of being tested at the test stage. In this manner, time can be saved in the testing of each of the integrated circuits that are to be tested.
Upon viewing the present disclosure, those skilled in the art will understand that many other disadvantages exist in the prior art.


REFERENCES:
patent: 4926117 (1990-05-01), Nevill
patent: 4945302 (1990-07-01), Janum
patent: 5278495 (1994-01-01), Beaton et al.
patent: 5610081 (1997-03-01), Ping et al.
patent: 5796246 (1998-08-01), Poh et al.

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