Maskless process for self-aligned contacts

Details Maskless process for self-aligned contacts Maskless process for self-aligned contacts

2000-01-21

2001-07-17

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S424000, C257S408000

Reexamination Certificate

active

06261924

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a maskless process for forming diffusion contacts which are self-aligned and borderless to both gate conductors and isolation regions.
2. Description of the Related Art
To manufacture semiconductor memories, for example, dynamic random access memories (DRAM) as inexpensively as possible, it is important that innovative processes which reduce the total number of masks be sought. In the prior art, source-drain (bitline-node) diffusion contacts are provided which are borderless to an adjacent gate structure (e.g., including a wordline). The process for forming these borderless contacts with respect to the gate requires the application of a critical mask.
It should be noted that the so called “borderless” diffusion contact of conventional DRAM processes is borderless only to the adjacent gate and does overlap adjacent isolation regions. Misalignment of the contact mask and an active area mask, combined with contact overetch into adjacent isolation regions, may result in a deeper than desired junction forming along the sidewall of the active area silicon. A deeper junction degrades the short channel characteristics of a transistor (e.g., a metal oxide semiconductor field effect transistor (MOSFET)) formed in the active area silicon and increases the overall variation in threshold voltage of the transistor.
An additional concern of conventional DRAM processes is the effect of silicon defects induced in the memory array by implanted source-drain diffusions. Since these defects aggravate junction leakage mechanisms (bulk, surface and gate induced drain leakage (GIDL)), the dose of the implanted impurity (typically phosphorus or arsenic) is limited to rather small values (for example, <1×10
14
cm
−2
). The low doses used for the array source-drain implants contribute to increased total series resistance, which degrades performance.
Therefore, a need exists for a self-aligned maskless contact fabrication process which prevents misalignment and reduces junction degradation and leakage problems.
SUMMARY OF THE INVENTION
A method for forming self-aligned borderless contacts without a masking process, in accordance with the invention, includes forming a shallow trench isolation region about an active area region and forming a gate structure through the active area region. The gate structure and shallow trench isolation region extend above a surface of a substrate, and the substrate has an exposed portion between the gate structure and shallow trench isolation region. Undoped polysilicon is deposited over the gate structure, the shallow trench isolation region and the exposed portion of the substrate. The polysilicon is removed from the gate structure and shallow trench isolation region, and remaining polysilicon is doped to form contacts in contact with the substrate.
In other methods, the step of forming a gate structure may include the steps of depositing a first dielectric layer on a surface of the substrate, forming a channel through the first dielectric layer down to the substrate and into the trench isolation region, forming a gate dielectric layer on the substrate in the channel, depositing a gate conductor on the gate dielectric layer in the channel, and forming a cap layer on the gate conductor in the channel.
The cap layer may include oxide and the step of forming a cap layer may include the step of depositing an oxide in the channel on the gate conductor and planarizing the oxide layer to form the cap layer. The first dielectric layer may include a nitride and the step of forming a second dielectric layer on the first dielectric layer may be included. The second dielectric layer may include a nitride.
In still other embodiments, the step of depositing a gate conductor on the gate dielectric layer in the channel may include the steps of depositing the gate conductor in the channels and over the second dielectric layer, planarizing the gate conductor from the second dielectric layer by employing the second dielectric layer as a polish or etch stop and recessing the gate conductor into the channel. The step of forming a gate structure may include the step of depositing an oxide on the gate conductor and etching the oxide to insulate sides of the gate conductor. The step of depositing an oxide may include the step of oxidizing the gate conductor to further insulate sides of the gate conductor. The step of forming diffusion regions in the active area may be included. The step of forming diffusion regions in the active area preferably include the step of outdiffusing dopants implanted in the contacts into the substrate to form the diffusion regions. The method may include the steps of forming an etch stop layer over the contacts, shallow trench isolation region and the gate structure, depositing an interlevel dielectric layer on the etch stop layer, etching holes or trenches in the interlevel dielectric layer corresponding to positions of the contacts, opening the etch stop layer over the contacts, and filling the holes or trenches with conductive material for electrically connecting to the contacts.
Another method for forming self-aligned borderless contacts without a masking process includes the steps of forming a shallow trench isolation region about an active area region, implanting wells in a substrate in the active area region, and forming a gate structure over the active area region. The gate structure and shallow trench isolation region extend above a surface of the substrate, and the substrate has an exposed portion between the gate structure and the shallow trench isolation region. Undoped polysilicon is deposited over the gate structure, the shallow trench isolation region and the exposed portion of the substrate. The polysilicon is removed from the gate structure and shallow trench isolation region, and the remaining polysilicon is doped to form contacts in contact with the substrate. Dopants are outdiffused from the contacts into the substrate to form source and drain diffusion regions.
In other methods, the step of forming a gate structure may include the steps of depositing a first nitride layer on a surface of the substrate, forming a channel through the first nitride layer region down to the substrate and into the shallow trench isolation, forming a gate oxide layer on the substrate in the channel, depositing a gate conductor on the gate oxide layer in the channel, and forming an oxide cap layer on the gate conductor in the channel. The may include the step of forming a second nitride layer on the first nitride layer. The step of depositing a gate conductor on the gate oxide layer in the channel may include the steps of depositing the gate conductor in the channels and over the second nitride layer, planarizing the gate conductor from the second nitride layer by employing the second nitride layer as a polish or etch stop, and recessing the gate conductor into the channel. The step of forming a gate structure may include the step of depositing an oxide on the gate conductor and etching the oxide to insulate sides of the gate conductor. The step of depositing an oxide may include the step of oxidizing the gate conductor to further insulate sides of the gate conductor. The method may include the steps of forming an etch stop layer over the contacts, shallow trench isolation region and the gate structure, depositing an interlevel dielectric layer on the etch stop layer, etching holes or trenches in the interlevel dielectric layer corresponding to positions of the contacts, opening the etch stop layer over the contacts, and filling the holes or trenches with conductive material for electrically connecting to the contacts.
Yet another method for forming self-aligned borderless contacts without a masking process includes forming raised structures above a surface of a substrate having an exposed portion of the substrate therebetween, depositing a conductive material over the raised structures and planarizing the conductive material from top surfaces of

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