Masked memory cells

Details Masked memory cells Masked memory cells

2011-03-01

2011-03-01

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Read only systems

Semiconductive

C365S189110, C365S189170

Reexamination Certificate

active

07898836

ABSTRACT:
An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.

REFERENCES:
patent: 6154384 (2000-11-01), Nataraj et al.
patent: 6496399 (2002-12-01), Choi et al.
patent: 6646900 (2003-11-01), Tsuda et al.
patent: 6760241 (2004-07-01), Gharia
patent: 6845025 (2005-01-01), Nataraj
patent: 7154764 (2006-12-01), Nataraj
patent: 2008/0205169 (2008-08-01), Kuenemund et al.

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