Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1997-12-16
2004-03-30
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C438S401000, C438S462000, C438S975000
Reexamination Certificate
active
06713883
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a mask set for compensating a misalignment between patterns and a method of compensating a misalignment between patterns using the same. In particular, the present invention relates to mask set for compensating for a misalignment between patterns and method of compensating for a misalignment between patterns using mask set.
2. Description of the Prior Art
Generally, in the process of manufacturing a semiconductor device, a mask process of ten through thirty steps is required in order to form an impurity diffusion region, a contact hole and a conductive pattern. As semiconductor devices become higher integrated, a process margin between the patterns becomes more narrow. In the lithography process of forming a contact hole or a conductive pattern during the process of manufacturing the semiconductor device, there occurs a misalignment between the underlying and the upper patterns due to a misalignment occurring when the mask and the wafer are loaded into the exposure equipment and an alignment error of the exposure equipment itself. Though it does not cause a problem when the process margin between the underlying pattern and the upper pattern is great, when a contact hole is formed between the underlying and the upper patterns when the process margin therebetween is small, these patterns are likely to be exposed or part of them are likely to be etched, thereby resulting in reduction of reliability of the semiconductor device.
In order to solve these problems, a conventional method is to insert an alignment mark into a mask and/or a wafer and then monitor the alignment mark at the exposure equipment so as to compensate for a misalignment of the mask and/or the wafer. Also an alignment error of the exposure equipment itself in the conventional method is obtained in such a manner that it selects the mask having smallest process margin between the patterns among the masks for use in the manufacture process of a semiconductor device, forms patterns on a test wafer through the lithography process using these masks, and measures the alignment accuracy by means of the optical methods such as SEM or TEM etc. However, the measured values by this method are different for each person since they are obtained by each person's baked eye and further the time taken to perform one-time measurement is too long, thus it is extremely difficult to obtain statistical data. Especially, it is usually difficult to use the test wafer once the alignment accuracy of which is measured for other purpose since the sample thereof must be cut away the wafer in order to take a photograph of the cross-sectional SEM.
SUMMARY OF THE INVENTION
It is an object of the present invention to method of compensating for a misalignment between patterns using three masks, which can measure electrically the alignment accuracy.
To achieve the above object, a mask set for compensating a misalignment between patterns comprises a first mask consisted of a mask substrate on which a main pattern and a plurality of sub-patterns are formed, a second mask consisted of a mask substrate on which a plurality of hole patterns are formed. The hole patterns of the second mask correspond to spaces between the main pattern and the sub-patterns of the first mask, respectively when the first and second mask are overlapped to each other.
The mask set further comprises a third mask consisted of mask substrate on which a plurality of bar patterns are formed, the bar patterns correspond to the hole patterns of the second mask, respectively when the second and third mask are overlapped to each other.
A method of compensating a misalignment between patterns, comprises the steps of forming a first test pattern and a plurality of second test patterns on a first insulating layer formed on a test wafer using a first mask; forming a second insulating layer on the first insulating layer including the first test pattern and the plurality of second test patterns and then forming contact holes between said the first test pattern and the plurality of second test patterns, respectively, using a second mask; forming third test patterns on the plurality of contact holes, respectively, using a third mask; measuring resistance using a resistance tester of which one terminal is connected to the first test pattern and another terminal is connected to the plurality of second test patterns one by one; and confirming a misalignment between the patterns using the measured resistance value.
REFERENCES:
patent: 4655598 (1987-04-01), Murakami et al.
patent: 4929083 (1990-05-01), Brunner
patent: 5308682 (1994-05-01), Morikawa
patent: 5672520 (1997-09-01), Natsume
patent: 5861679 (1999-01-01), Nagano
Hong Soon Won
Yang Tae Hum
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Wilson Allan R.
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