Mask-saving technique for forming CMOS source/drain regions

Details Mask-saving technique for forming CMOS source/drain regions Mask-saving technique for forming CMOS source/drain regions

1981-10-15

1983-09-27

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 148187, 357 91, H01L 21265, B01J 1700

Patent

active

044067100

ABSTRACT:
CMOS source/drain regions of both conductivity types are formed using only a single masking step. One dopant is applied to both types of source/drain regions, and a second dopant is applied at a much higher dose and energy to only one type of source/drain region.
Preferably, boron and arsenic are used as the dopants in silicon, since the cooperative doping effect causes the boron in the counterdoped source/drain regions to be entirely contained within the arsenic diffusion.

REFERENCES:
patent: 3920481 (1975-11-01), Hu
patent: 4108686 (1978-08-01), Jacobus, Jr.
patent: 4244752 (1981-01-01), Henderson, Sr. et al.
patent: 4306916 (1981-12-01), Wollesen et al.
patent: 4315781 (1982-02-01), Henderson
patent: 4335504 (1982-06-01), Lee
Fair, R. B., Solid State Electronics, 17 (1974), 17 Beanland in Ion Implantation in Semiconductors, 1976, ed. Chernow et al., Plenum, N.Y., 1977, p. 31.

Affiliated with

Also associated with

Rating

Mask-saving technique for forming CMOS source/drain regions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Mask-saving technique for forming CMOS source/drain regions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mask-saving technique for forming CMOS source/drain regions will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2129378