Mask ROM-type semiconductor memory device

Details Mask ROM-type semiconductor memory device Mask ROM-type semiconductor memory device

1981-12-16

1985-02-19

Richardson, Robert L.

Static information storage and retrieval

Read only systems

Semiconductive

G11C 1140

Patent

active

045009759

ABSTRACT:
A plurality of MIS-type transistors are arranged in a matrix, with each one of these MIS-type transistors corresponding to one memory information bit. These MIS-type transistors are formed so as to store and read binary information in accordance with whether the characteristic of these MIS-type transistors is normally on or normally off. At least one of the source and drain regions of the MIS-type transistors having a normally on characteristic is formed with a higher impurity density or at a greater depth compared with the regions of the MIS-type transistors having a normally off characteristic.

REFERENCES:
patent: 4074238 (1978-02-01), Masuda
patent: 4081794 (1978-03-01), Parks et al.
IBM Technical Disclosure Bulletin, "FET Array Personalization by Ion Implantation" by R. W. Knepper, vol. 15, No. 9, Feb. 1973, pp. 2919-2920.
IBM Technical Disclosure Bulletin, "Self-aligned Polysilicon Gate MOSFETS with Tailored Source and Drain Profiles", Bassous et al., vol. 22, No. 11, 4/1980.

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