Mask-ROM manufacturing method that enhances integration density

Details Mask-ROM manufacturing method that enhances integration density Mask-ROM manufacturing method that enhances integration density

1990-08-15

1991-03-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 49, 437 50, 437 52, 357 235, 357 236, 365103, 365104, 365185, H01L 2100, H01L 2102, H01L 21265, B01J 1700

Patent

active

050028960

ABSTRACT:
A manufacturing method of a mask-ROM of two-layered gate electrode structure is provided. With this method, a cell transistor having a first-layered gate is converted into the depletion type according to data to be stored in the following manner. That is, a first conductive layer is insulatively formed over a semiconductor substrate of a first conductivity type, a silicon nitride film is formed on the first conductive layer, a polysilicon film is formed on the silicon nitride film, the polysilicon film is patterned and then altered into a silicon oxide film so as to increase its volume, and the silicon nitride film is patterned with the silicon oxide film used as a mask to form windows for permitting impurity to be doped therethrough. Then, impurity for converting cell transistors into the depletion type according to data to be stored is doped from the windows into the substrate through the first conductive layer.

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