Mask ROM

Details Mask ROM Mask ROM

2003-03-13

2004-12-14

Mai, Son (Department: 2818)

Static information storage and retrieval

Read only systems

Semiconductive

C365S096000, C257S390000, C257S401000

Reexamination Certificate

active

06831851

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a mask-type programmable read-only memory (ROM), and more particularly relates to a high density mask-type programmable read-only memory having word lines that are arranged in a grid manner, while the bit lines are parallel with the diagonal line of the memory units array, and the bit lines join the drains obliquely.
2. Description of the Related Art
Read-only memory (ROM) devices are semiconductor integrated circuits widely used in microprocessor based systems to permanently store information even when the power is off. ROM devices are particularly well suited for applications where a large volume of devices having identical data are required or for storing data that is repeatedly used. Therefore, the mask of the mask ROM is changed only when the product is different, and the manufacturing process of the Mask ROM is not modified in greater part.
Conventional mask ROM includes NOR-type and NAND-type. NOR-type ROM is formed by connecting in parallel the sources and the drains of the memory transistors. Alternatively, connecting the sources and the drains of the memory transistors in series forms a NAND-type ROM.
A 4×4 memory unit array is shown in
FIG. 1
, wherein the Mask ROM includes a row decoder
101
, a column decoder
102
, and a memory unit array
103
. The row decoder
101
receives a row address value
104
; and the column decoder
102
receives a column address value and output a value
106
.
The memory array
103
comprises sixteen transistors
111
to
144
, four bit lines, and four word lines. The four bit lines are C
1
, C
2
, C
3
, and C
4
, which connects to the column decoder
102
. The four word lines are R
1
, R
2
, R
3
, and R
4
, which connect to the row decoder
101
.
The bit lines are connected to the transistors by a filled inter layer as shown in
FIG. 1
, wherein a black point represent a connective node. A transistor is not connected without a black point.
A volt direct current is also connected to the transistor (not shown), and the volt direct current is a low voltage which represents a logic value “0”.
The operation of the transistor is described as follow.
In the initial stage, the voltages of the word lines are lower than the threshold voltage, so that all of the transistors are OFF in the memory. The voltage is high of the bit lines which represent a logic value “1”.
At first, the row decoder
101
receives a row address value
104
, and the row address value
104
is decoded. According to the decoded result, one of the word lines R
1
, R
2
, R
3
, and R
4
is selected to raise the voltage value, and the transistors which connects with the selected bit line are ON.
When the word line R
1
is the selected one, the transistors
111
,
112
,
113
, and
114
are ON. The bit lines C
1
, C
3
, and C
4
are connected with the transistors
111
,
113
, and
114
, so that the logic value of the C
1
, C
2
, C
3
, C
4
output is 0, 1, 0, 0.
When the word line R
2
is the selected one, the transistors
121
,
122
,
123
, and
124
are ON. The bit lines C
1
and C
3
are connected with the transistors
121
and
123
so that the logic value of the C
1
, C
2
, C
3
, C
4
output is 0, 1, 0, 1.
When the word line R
3
is the selected one, the transistors
131
,
132
,
133
, and
134
are ON. The bit lines C
2
and C
4
are connected with the transistors
132
and
134
, so that the logic value of the C
1
, C
2
, C
3
, C
4
output is 1, 0, 1, 0.
When the word line R
4
is the selected one, the transistors
141
,
142
,
143
, and
144
are ON. The bit lines C
1
, C
2
, C
3
, and C
4
are connected with the transistors
141
,
142
,
143
, and
144
, so that the logic value of the C
1
, C
2
, C
3
, C
4
output is 0, 0, 0, 0.
Next, the column decoder
102
receives a column address value
105
so as to select one of the bit lines to output an output value
106
.
There are 16 logic values in all of the groups (0, 1, 0, 0), (0, 1, 0, 1), (1, 0, 1, 0) and (0, 0, 0, 0). The column decoder
102
selects one of the groups (0, 1, 0, 0), (0, 1, 0, 1), (1, 0, 1, 0) and (0, 0, 0, 0) to output an output value
106
according to the row address value
104
.
In
FIG. 2
, there is a plurality of memory units, and each memory unit comprises a source
201
, a drain
202
, a plurality of word lines
203
and plurality of bit lines
204
. The word lines
203
are parallel to each other and the bit lines
204
are parallel to each other and the bit lines
204
and thw word line
203
are perpendicular to each other. The sources
201
and the drains
202
are alternatively arranged in a line manner respectively, and the sources
201
and the drains
202
are arranged on the grids comprising the word lines
203
and the bit lines
204
.
The word lines
203
which control a specific memory unit are conducted first, and then the bit lines
204
connected to the specific memory are coupled, and the memory unit is read.
Each drain and adjacent two sources consist of two memory units or each source and adjacent two drains consist of two memory units of the conventional Mask ROM.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide a Mask ROM, in which the arrangement of the memory array has increased memory units densely in the Mask ROM.
The present invention provides a mask ROM comprising a plurality of word lines, a plurality of memory units, a plurality of first bit lines, a plurality of second bit lines, a plurality of first nodes, a plurality of second nodes, a plurality of third bit lines, and a plurality of fourth bit lines.
The memory units are arranged between the word lines and each memory unit is provided with a corresponding drain. The first bit lines are arranged in parallel and extending in a direction diagonal to the word lines and above the drains. The second bit lines are arranged in parallel and extending in a direction diagonal to the word lines, and above the drains. The first nodes are alternately arranged on the first bit lines. The second nodes are alternately arranged on the second bit lines, and the second nodes and the first nodes are alternated. The third bit lines are joined to the first bit lines and the fourth bit lines are joined to the second bit lines.
The present invention also provides a mask ROM comprising a memory unit array, a plurality of first bit lines, a plurality of second bit lines, a plurality of third bit lines, and a plurality of a fourth bit lines.
The memory unit array comprises a plurality of word lines and a plurality of memory units, wherein the word lines are arranged in a grid manner, and each memory unit is provided with a corresponding drain. The first bit lines are arranged in parallel and extending in a direction diagonal to the word lines and above the drains, wherein the drains are coupling or noncoupling with the bit lines which correspond to the drain on both sides of each word line. The second bit lines are arranged in parallel and extending in a direction diagonal to the word lines and above the drains, wherein the drains are coupling or noncoupling with the bit lines which correspond to drain on the both sides of each word line. The third bit lines are joined to the first bit lines and the fourth bit lines are joined to the second bit lines.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 5250831 (1993-10-01), Ishii
patent: 5332923 (1994-07-01), Takeuchi
patent: 5864496 (1999-01-01), Mueller et al.
patent: 2003/0202397 (2003-10-01), Saito et al.

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