Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
1999-02-18
2001-01-16
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S601000, C148SDIG005
Reexamination Certificate
active
06174753
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This invention is related to co-filed U.S. Patent application entitled “Mask Reduction Process with a Method of Forming an Embedded Fuse and a Fuse Window with Sidewall Passivation” assigned to same assignee with a common inventor as the present application and incorporated herein by reference in their entirety.
FIELD OF THE INVENTION
The present invention relates to semiconductor fabrication processes, and more specifically, to a mask reduction process with a method of forming a raised fuse and a fuse window with sidewall passivation.
BACKGROUND OF THE INVENTION
The design concept of making redundant cells or circuits to replace defective ones is of vital application in the fabrication of integrated circuits. Defective cells on a chip are usually identified using a chip probe test step after wafer processing. The defective cells can be replaced with redundant cells by the redefinition of connective paths. With such a reworking process to correct fabrication defects, the number of defective cells can be greatly reduced. The use of redundant cells is employed in most memory chips and logic circuit chips to increase the yield and reduce the cost of production.
There are several ways of modifying the connections to substitute redundant cells for defective cells. The use of a fuse is one of the most widely employed methods for swapping defective cells with redundant cells. The replacement of defective cells is achieved by breaking the appropriate fuses on the chip. The conducting paths are then changed to address the defect free redundant cells. Typically, a laser is applied to “blow” the fuse with the predetermined address code.
Taking a DRAM memory array as an example, one or more spare rows and columns are formed outside or around the designed memory array. In general, fuse connections are formed with the poly-1 (the first polysilicon layer) and poly-2 (the second polysilicon layer) of the interconnection structures. A defective cell with an identified address can be replaced by blowing the corresponding fuse to connect a redundant cell.
Referring to
FIG. 1
, a fuse window
10
is opened during manufacturing. This is also referred to as the laser window. The fuse window
10
is opened by removing dielectric layers or passivations layers
26
,
12
,
14
, and
16
over the fuse
18
in the manufacturing process. Thus the fuse
18
can be readily reached by the laser beam to blow it out.
For reducing the complicate masking and etching process needed for forming fuse window after the formation of metal lines, a fuse window opening can be modified to be formed simultaneously with the inter-metal contact via holes. However, the formation of fuse window or fuse window opening
10
by removing the dielectric or the passivation layers
26
,
12
,
14
, and
16
may cause some problems. The fuse window
10
, which is opened across several layers of dielectric materials, makes the interface regions
10
a
and
10
b
between the dielectric or the passivation layers
12
,
14
, and
16
to be exposed. It has been found that moisture and contamination from outside can enter into the conductive paths
20
,
22
, and
24
through the interface regions
10
a
and
10
b
. The diffused moisture can further reach the elements or connections of the devices on the substrate. By reacting with moisture and contamination, the conductive structures and other elements are corroded to cause functional degradation or damage. The reliability and yield of the products are then decreased.
In the conventional process of forming fuse window, a dielectric layer is left over the fuse
18
. The dielectric layer is mostly a transparent oxide layer of several thousand angstrom thickness. During the laser repairing process (the act of blowing the fuses), the fuse
18
is melted and the oxide layer is exploded. A greater energy is required to explode the oxide layer to ensure an exact breakdown of the fuse
18
. A laser using a higher energy is harder to control accurately. Additionally, when the fuse is blown, residue from the fuse may leak to surrounding structures and decreases the reliability of the reworking process.
What is needed is a mask reduction process with a method of forming a raised fuse and a fuse window with sidewall passivation. A raised fuse structure that is easily broken is also needed for providing a low energy and easily controlled laser reworking process.
SUMMARY OF THE INVENTION
A method of forming a raised fuse structure with sidewall-protected fuse window on a substrate is disclosed. The method comprises the steps of: removing a portion of said dielectric layers to form an inter-metal contact via hole within said dielectric layers extending down to said first conductive structure and to form simultaneously a fuse opening within said dielectric layers over said fuse; forming a second conductive structure within said inter-metal contact via hole and over said inter-metal contact via hole; forming a passivation layer over said second conductive structure and said fuse opening; and removing a portion of said passivation layer and of said dielectric layers down to at least said fuse for forming said fuse window between a sidewall structures formed on said fuse opening and for leaving an raised fuse structure.
REFERENCES:
patent: 5578517 (1996-11-01), Yoo et al.
patent: 5753539 (1998-05-01), Okazaki
patent: 5930664 (1999-07-01), Hsu et al.
patent: 5965927 (1999-10-01), Lee et al.
patent: 6004834 (1999-12-01), Tsukude et al.
patent: 6096579 (2000-08-01), Liao et al.
Christensen O'Connor Johnson PLLC
Picardat Kevin M.
Vanguard International Semiconductor Corporation
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