Mask read-only memory and fabrication thereof

Details Mask read-only memory and fabrication thereof Mask read-only memory and fabrication thereof

2002-04-25

2004-03-30

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S636000, C438S736000, C257S437000

Reexamination Certificate

active

06713315

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 91105147, filed Mar. 19, 2002.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a structure of a read-only memory (ROM) and the fabrication thereof More particularly, the present invention relates to a structure of a mask read-only memory (Mask ROM) and the fabrication thereof.
2. Description of Related Art
The read-only memory (ROM) is non-volatile, which means that the data stored in it does not disappear when the power is switched off, and is therefore used in many electronic products for storing booting data and system parameters, etc. The simplest ROM is namely the Mask ROM, which uses MOS transistors as memory cells and is programmed by implanting ions into the channel regions of selected memory cells. The threshold voltages of the memory cells are therefore selectively changed and the On/Off states of the memory cells during a reading operation are thereby controlled.
A typical Mask ROM has a plurality of polysilicon word-lines (WL) crossing over a plurality of buried bit-lines in a substrate, whereby a channel region is defined in the substrate under a word-line and between two buried bit-lines. In some cases, the logic state of a Mask ROM cell is 0 or 1 dependent on the presence or the absence of the ions implanted, which is determined by a coding implantation process.
Refer to
FIG. 1
,
FIG. 1
schematically illustrates a top view of a conventional Mask ROM. As that shown in
FIG. 1
, the Mask ROM has a plurality of parallel wordlines
102
crossing over a plurality of parallel buried bit-lines
104
. The Mask ROM is programmed by implanting ions into a selected channel region
110
in the substrate to control the threshold voltage and the logic state of the selected Mask ROM cell.
Refer to
FIG. 2
,
FIG. 2
schematically illustrates a coding process of the conventional Mask ROM in a cross-sectional view. As that shown in
FIG. 2
, a plurality of gate structures
206
each comprising a gate dielectric layer
202
and a gate conductive layer
204
are located on a substrate
200
. A plurality of buried bit-lines
208
are located in the substrate
200
between the gate structures
206
and an insulating layer
210
is disposed covering the buried bit-lines
208
. In a subsequent coding process, a patterned photoresist layer
212
not covering a selected channel region is formed over the substrate
200
by using a photo mask. An implantation
214
is then performed to dope the selected channel region with the photoresist layer
212
as a mask.
Since a conventional Mask ROM is programmed by selectively doping the channel regions of the memory cells in the front-end process described above, the fabricating process of the semi-finished Mask ROM products have to be stopped in the front-end process. Therefore, when an order is received, quite a few fabricating steps are required to finish the Mask ROM products before packing and delivering them to the client. Consequently, it takes much time to finish a conventional Mask ROM after an order is received and a special coding mask (e.g. a patterned photoresist layer) is needed for the coding implantation. Moreover, the opening in the patterned photoresist layer is easily mis-aligned with the selected channel region to cause data errors and therefore lower the reliability of the product.
SUMMARY OF THE INVENTION
Accordingly, this invention provides a Mask ROM and a method for fabricating a Mask ROM in order to prevent data errors in the Mask ROM.
This invention also provides a Mask ROM and a method for fabricating a Mask ROM in order to save a special coding mask.
This invention further provides a Mask ROM and a method for fabricating a Mask ROM in order to decrease the time required for finishing the product after an order is received.
In the method for fabricating a Mask ROM of this invention, a charge trapping layer (e.g., a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer) and a plurality of gate structures are formed on a substrate, wherein the charge trapping layer under each gate structure serves as a predetermined coding region. A plurality of bitlines are formed in the substrate between the gate structures and a plurality of wordlines are formed over the substrate to electrically connect with the gate structures. An material layer capable of blocking UV light (e.g., a chemical vapor deposition antireflective coating (CVD-ARC)) having coding windows therein and an inter-layer dielectric layer are formed over the substrate. A coding process is then performed by using UV light to form a plurality of charged coding regions in the charge trapping layer under the coding windows. A plurality of plugs are then formed in the coding windows.
The Mask ROM of this invention comprises a substrate, a charge trapping layer, a plurality of gate structures, a plurality of bit-lines, a plurality of word-lines, a material layer capable of blocking UV light (e.g., a CVD-ARC), an inter-layer dielectric layer, and a plurality of plugs. The charge trapping layer is located on the substrate and the gate structures are located on the charge trapping layer, wherein the charge trapping layer under each gate structure serves as a coding region. The bit-lines are located in the substrate between the gate structures. The word-lines are located over the substrate and are electrically connected with the gate structures. The material layer is located over the substrate and the inter-layer dielectric layer is located on the material layer. The plugs are embedded in the inter-layer dielectric layer and the material layer and are located over some of the coding regions.
In the Mask ROM process of this invention, the charge trapping layer is used as the coding regions, the material layer capable of blocking UV light as a coding mask, and UV light as a programming tool. When the coding windows are being formed in the inter-layer dielectric layer and the material layer, contact holes can be form simultaneously in the inter-layer dielectric layer in a periphery region of the Mask ROM. Therefore, the coding window process can be integrated with the contact hole process and a special coding mask (e.g. a patterned photoresist layer) can be saved to reduce the production time and the production cost.
Moreover, since the coding window process can be integrated with the contact hole process in this invention, the Mask ROM process can be stopped before the contact hole process (a back-end process). After an order is received, the contact hole process and the coding window process are performed simultaneously. Consequently, the time required for finishing the products after an order is received can be reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5710067 (1998-01-01), Foote et al.
patent: 5977601 (1999-11-01), Yang et al.
patent: 6274445 (2001-08-01), Nouri
patent: 2003/0100158 (2003-05-01), Huang

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