Mask programmable read-only memory (ROM) cell

Details Mask programmable read-only memory (ROM) cell Mask programmable read-only memory (ROM) cell

2003-05-06

2004-10-26

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Read only systems

Fusible

C365S094000, C365S225700, C365S103000, C365S104000

Reexamination Certificate

active

06809948

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for programming a memory cell by changing the state of a material, such as an anti-fuse element, in a MOS-based programmable memory. The present invention also relates to a multi-bit programmable memory cell that includes a plurality of anti-fuse elements.
RELATED ART
FIG. 1
is a cross sectional view of a conventional anti-fuse element
100
, which includes first metal layer
101
, second metal layer
102
, inter-metal dielectric layer
103
, metallic plug
104
, and amorphous silicon layer
105
. Metallic plug
104
, which is located in a via in inter-metal dielectric layer
103
, contacts first metal layer
101
. Amorphous silicon layer
105
is located between metallic plug
104
and second metal layer
102
. A titanium nitride barrier layer (not shown) may be located between amorphous silicon layer
105
and second metal layer
102
. As deposited, amorphous silicon layer
105
is an insulator. However, after a sufficiently high voltage is applied across amorphous silicon layer
105
, a conducting channel is formed in the amorphous silicon. For example, a voltage of about 5 Volts is sufficient to create a conducting channel in an amorphous silicon layer having a thickness of 100 Angstroms. The conducting channel created through layer
105
is permanent, with the resistance of this conducting channel being determined by the programming current. The relationship between the resistance (R) of the conducting channel and the programming current (I
PROGRAM
) is defined as follows.
R=K
FUSE
/I
PROGRAM
.
The value of K
FUSE
is approximately 0.75. Thus, a programming current of 15 mA would result in a conducting channel having an on-resistance (R) of about 50 Ohms. As long as the subsequently applied currents are much smaller than the programming current (i.e., about 50 to 20 percent of the programming current or less), the on-resistance (R) will remain constant.
FIG. 2
is a circuit diagram of a conventional programmable read-only memory array
200
that uses anti-fuse elements. PROM array
200
includes PROM cells
201
-
208
, word lines
211
-
212
, source line
215
and bit lines
221
-
224
. Each of PROM cells
201
-
208
includes a transistor and a corresponding anti-fuse element. Thus, PROM cells
201
-
208
include n-channel transistors
231
-
238
and anti-fuse elements
241
-
248
, as illustrated. Although
FIG. 2
illustrates a 2×4 array, it is understood that a typical PROM array will have a larger number of rows and columns.
Each of the PROM cells
201
-
208
can be programmed by applying a relatively large programming current through the anti-fuse element of the PROM cell. For example, a programming current can be applied to anti-fuse element
241
of PROM cell
201
by applying a high programming control voltage to word line
211
and a high programming voltage across bit line
221
and source line
215
. The required programming current determines the required width of the corresponding transistor. Thus, if the anti-fuse elements are designed to be programmed in response to a programming current of 1 mA, then the width of the corresponding transistors must be sized to handle this 1 mA programming current. For example, a transistor having a 0.24 micron gate length is capable of handling 590 microAmps of current for each micron of width under nominal 2.5 Volt saturation conditions. Such a transistor must have a channel width of 1.7 microns to handle a 1 mA programming current. Using conventional 0.18 micron design rules, the resulting PROM cell will have a width of about 1.92 microns and a length of about 1.08 microns, or about 2.07 microns/bit. In contrast, a transistor designed at the design rule minimum using a 0.18 micron process is capable of handling a current of about 225 microAmps, and has a cell size of about 0.6 microns wide by about 1.08 microns long.
Alternative materials, such as mixed chalcogenides, have also been used as an anti-fuse material. Examples of mixed chalcogenides are described in U.S. Pat. No. 3,271,591 (Ovshinsky, 1966), U.S. Pat. No. 3,675,090 (Neale, 1972) and U.S. Pat. No. 5,166,758 (Ovshinsky, et al., 1991).
If the anti-fuse material characteristics or the circuit requirements dictate a programming current that is larger than the capability of a minimum sized device, it would be desirable to have a way of increasing the programming current without a commensurate increase in the memory cell size.
SUMMARY
Accordingly, the present invention provides a multi-bit memory cell that includes an access transistor and a plurality of N anti-fuse elements (where N is an integer greater than 1). The access transistor has a source coupled to a source line and a gate coupled to a word line. Each of the anti-fuse elements has a first terminal coupled to a drain of the access transistor, and a second terminal coupled to a corresponding bit line. Initially, all of the N anti-fuse elements are unprogrammed (open). At most, one of the N anti-fuse elements is programmed. Thus, the programmable memory cell is capable of storing (N+1) states. Consequently, the memory cell is cable of storing M binary bits, where 2
M
=N+1. For example, a memory cell that uses three anti-fuse elements (N=3) is capable of storing 2 binary bits.
The access transistor is sized to provide a programming current sufficient to program any one of the N anti-fuse elements. For example, the access transistor may be sized to provide a drive current of 1 mA. In this example, the memory cell of the present invention would have a similar layout area as a conventional PROM cell. However, the memory cell of the present invention (which stores M bits) would have a per bit area that is M times less than the per bit area of a conventional PROM cell. In one embodiment, the multi-bit memory cell of the present invention is implemented in an array. In a particular embodiment, this array can have in excess of 100,000 transistors, organized into rows accessed by word lines and columns connected by bit lines.
Another embodiment includes a method for operating the multi-bit programmable memory cell, which includes (1) programming one or none of the N anti-fuse elements of the memory cell, (2) applying a read voltage to a first terminal of each of the N anti-fuse elements through the access transistor, (3) sensing the signals on the second terminals of the N anti-fuse elements while the read voltage is applied to the first terminals, and (4) decoding the signals sensed on the second terminals of the N anti-fuse elements, thereby providing M decoded data signals.
The present invention will be more fully understood in view of the following description and drawings.


REFERENCES:
patent: 3271591 (1966-09-01), Ovshinsky
patent: 3629863 (1971-12-01), Neale
patent: 3675090 (1972-07-01), Neale
patent: 4609998 (1986-09-01), Bosnyak et al.
patent: 5166758 (1992-11-01), Ovshinsky et al.
patent: 5233217 (1993-08-01), Dixit et al.
patent: 5299150 (1994-03-01), Galbraith et al.
patent: 5341328 (1994-08-01), Ovshinsky et al.
patent: 5469109 (1995-11-01), Paivinen
patent: 5886392 (1999-03-01), Schuegraf
patent: 5936832 (1999-08-01), Saito et al.
patent: 6154054 (2000-11-01), Shroff et al.

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