Mask pattern transfer method, mask pattern transfer...

Details Mask pattern transfer method, mask pattern transfer... Mask pattern transfer method, mask pattern transfer...

2000-02-07

2003-05-06

Anderson, Bruce (Department: 2881)

Radiant energy

Irradiation of objects or material

Irradiation of semiconductor devices

C250S492200, C250S492230, C250S491100, C250S398000, C250S3960ML, C250S400000

Reexamination Certificate

active

06559463

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to charge-beam exposure in lithography for semiconductor device manufacture.
An optical stepper with superior productivity has been used at the mass production stage of semiconductor memory device manufacture. For the production of memory devices from 1 GDRAM and 4 GDRAM downward having a line width of 0.2 &mgr;m or less, an electron-beam exposure method having a high resolution and superior in productivity is expected as one of exposure arts suitable for an optical exposure method.
Conventional electron-beam exposure methods mainly use a single-light-beam Gaussian method and a variable forming method. However, because these methods are inferior in productivity, they have been used for such purposes making good use of a superior resolution characteristic of the electron beam as mask drawing, research and development of VLSIs, and exposure of ASIC devices according to small-scale production.
Thus, to apply the electron beam exposure method to mass production, how to improve the productivity is a large problem. In the case of a conventional electron-beam aligner, however, an exposure area of an electronic optical system that can be exposed through one shot is extremely small compared to an exposure area of a projection optical system of an optical aligner. Therefore, to expose a wafer, because electronic and mechanical scanning distances increase compared to those of an optical aligner, a lot of time is required and throughput is extremely lowered. To improve the throughput, it is necessary to greatly accelerate electronic scanning and mechanical scanning or expand an exposure area for one shot.
To improve the throughput while keeping a necessary resolution, a method of forming a circuit pattern to be exposed on a silicon wafer as a mask, applying an electron beam whose exposure area is expanded to the mask, and transferring the mask pattern onto the wafer is studied. An electron-beam mask used for an electron-beam aligner usually has a circuit pattern 2 to 5 times larger than a circuit pattern on a silicon wafer, depending on a projection-system magnification of an electron-beam aligner. For example, it is said that a circuit pattern of one chip of a 4 Gbit-DRAM requires an area of approx. 20 mm×35 mm. A circuit pattern area on a mask for exposing the circuit pattern requires 80 mm×140 mm when a projection-system magnification is ¼. As shown in
FIG. 26A
, it is difficult to form a chip pattern (thin film portion)
600
having the above size enclosed by a beam portion
601
in a thin-film window on a mask
602
at a high-enough strength and accuracy. Therefore, as schematically shown in
FIG. 26B
, a structure is used in which the chip pattern
600
is divided into a plurality of portions and a reinforcement beam
603
is set between divided patterns.
FIG. 27A
shows a perspective view of an example of the above electron-beam mask and
FIG. 27B
shows a sectional view of the mask.
A plurality of mask pattern areas
501
are formed on a mask substrate
502
fixed onto a mask stage
506
and a portion between mask pattern areas
501
is reinforced by a reinforcement beam
505
.
The mask pattern area
501
is formed by patterning an electron-beam scatterer (high scatterer)
504
having a W of 0.02 &mgr;m on an electron-beam passing film (low scatterer)
503
(
FIG. 27B
) serving as a membrane made of SiN having a thickness of 0.15 &mgr;gm formed on the mask substrate
502
of a silicon wafer having a thickness of, for example, 2 mm. Because it is difficult to handle the silicon wafer alone, it is fixed to a mask stage
506
used for X-ray exposure.
FIG. 28
shows an example of a conventional transfer system for transferring divided mask patterns.
An electron beam
510
emitted from an electron source
501
is converged by a first condenser lens
511
and shaped into a rectangular electron beam by a forming aperture
502
. The shaped electron beam
510
is formed into an almost parallel electron beam by a second condenser lens
512
and applied to a mask
505
. The mask
505
is mounted on a mask stage
506
and continuously moved together with the mask stage
506
(this movement direction is assumed to be the x direction). The electron beam
510
passing through the mask
505
is contracted and transferred to a wafer
508
mounted on a wafer stage
509
continuously moving in the opposite direction to the mask stage
506
by a first projection lens
513
and a second projection lens
514
.
FIG. 29
shows how divided chip patterns on the mask
505
are transferred onto the wafer
508
.
The mask stage
506
moves from the electron beam
510
stopping under exposure along an arrow E shown at the top right in
FIG. 29. A
group of divided chip patterns on the mask
505
to which the electron beam
510
is applied due to one-time movement of the mask stage
506
in the X direction is referred to as a divided chip pattern on a stripe. For example, divided chip patterns M
11
, M
12
, . . . , and M
16
are present on the same stripe.
Moreover, the mask stage
506
and wafer stage
509
move synchronously each other. The wafer stage
509
is moved along an arrow Fat the bottom right in FIG.
29
. Furthermore, patterns between stripes are connected so that beams between stripes on the mask
505
do not appear on contracted patterns on the wafer stage
508
by moving the mask stage
506
and wafer stage
509
to the first pattern of each stripe. Patterns M
11
, M
12
. . . on the mask
505
are contracted on the wafer
508
and transferred as W
11
, W
12
. . . .
FIGS. 30A
to
30
E show states of transferring a divided pattern M
26
and a divided pattern M
25
on the mask
505
having a beam width S
56
in FIG.
29
.
In
FIGS. 30A
to
30
E, symbol B denotes a light beam, BA denotes a light-beam optical axis, an arrow M denotes a moving direction of a mask, and an arrow denotes a moving direction of a wafer, and the arrow M and arrow W show directions opposite to each other.
Exposure of the divided pattern M
26
onto the wafer
508
is started (
FIG. 30A
) and the divided pattern M
26
is exposed onto the wafer
508
as a divided pattern W
26
to be transferred in accordance with the relative movement between the mask
505
and the wafer
508
(
FIG. 30B
) When every divided pattern M
26
is exposed on the wafer
508
as the divided pattern W
26
to be transferred, exposure of the divided pattern M
26
is completed (FIG.
30
C). Then, exposure of the divided pattern M
25
onto the wafer
508
is started as a divided pattern W
25
to be transferred (
FIG. 30D
) and exposure of the next divided pattern M
25
is exposed similarly to the exposure of the divided pattern M
26
(FIG.
30
E).
However, the above transfer method has the following problem.
That is, as clarified from the description about the illustration of the chip
3
on the wafer
508
in FIG.
29
and
FIGS. 30A
to
30
E, beams shown by s
12
, s
23
, s
34
, s
45
, and s
56
in
FIG. 29
present between divided patterns on the same stripe on the mask
505
are left on the wafer
508
as gaps shown by SW
12
, SW
23
, SW
34
, SW
45
, and SW
56
, all divided patterns are connected, and thereby a transferred pattern shown in
FIG. 31
necessary for a chip pattern circuit to normally operate cannot be realized.
To solve the above problem, a method of repeatedly stopping and moving a wafer stage depending on a light-beam position on a mask while continuously moving a mask stage is considered. This is a method of moving a wafer stage when a light beam is present on a divided pattern on a mask on the same stripe but stopping the wafer stage when the light beam is present on a beam portion between divided patterns to remove the gaps s
12
, s
23
, s
34
, s
45
, and s
56
from a wafer. According to the above method, it may be possible to connect divided patterns on a wafer as shown in FIG.
31
. However, it is very difficult to practically use the above method because in the case of the mechanical connection control, a pattern connection accuracy is lowered due to

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