Mask pattern preparing method and photomask

Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask

Reexamination Certificate

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C430S030000

Reexamination Certificate

active

06180293

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for preparing a mask pattern and a photomask prepared by the method above.
With a recent advance toward a high integration of LSIs, a transfer pattern has been more and more miniaturized. That is, a recent tendency has been toward the use of short wavelength of a light source in an exposure apparatus, the use of a high numerical aperture in an optical projection system, the use of a high resolution resist, the use of a super resolution technique, etc. By the use of such techniques, a pattern which is very fine from an optical viewpoint in comparison with a conventional pattern, that is, a pattern which is low in a k1 value, can be transferred onto a wafer, noting that the k1 value denotes a value normalized by &lgr;/NA where &lgr;: a light exposure wavelength and NA: the numerical aperture. In the case where such a low-k1 pattern is transferred onto the wafer, an optical proximity effect (OPE), that is, a displacement of a transfer pattern from a desired pattern caused by a pattern arrangement, etc., becomes prominent. In recent years, investigation has been conducted on the use of an optical proximity correction (OPC) as a technique for obtaining a transfer pattern, as desired, on the wafer by considering such optical proximity effect at a designing stage and initially correcting an associated mask.
One OPC method is by finding an optical image on a wafer by virtue of a photolithography computation and calculating an amount of displacement between a desired pattern and a transfer pattern on the basis of the optical image found. With respect to the optical proximity effect resulting from an optical system and resist process, it is only necessary to perform computation on an area in a radius range of below 1 to 2 &mgr;m. If, on the other hand, a finishing configuration, after etching, is made to have a desired configuration, calculation is required in a range of about a few &mgr;m to several tens of &mgr;m.
Design data as a correction target often takes a form such that the same pattern is repeatedly arranged. In this case, the data structure is divided into drawing information (apex coordinate information) and array information of the same pattern, so that it is possible to largely compress the data amount. In a memory device such as a DRAM, therefore, a data hierarchical structure is often deep.
FIG. 7
shows a practical model as a basic hierarchical structure where the same cells are arranged in a given array. In this practical structure, an intermediate layer cell is comprised of (2×2) lowest layer cells and a highest layer cell is comprised of such intermediate layer cells, that is, (4×4) intermediate layer cells. If, in order to set the finishing configuration, after etching, in a desired state, the optical proximity correction is done on such data while consideration is given up to the etching, a larger portion of such a layer structure of the design data is flattened.
If the optical proximity correction is made in a range of a few &mgr;m to a few tens of &mgr;m while consideration is given up to the etching, then a problem arises, such as it will be very difficult to prepare a mask because associated data is explosively grown.
BRIEF SUMMARY OF THE INVENTION
The present invention is achieved with the above-mentioned task in view and it is accordingly the object of the present invention to provide a method for preparing a mask pattern and a photomask which can suppress a data amount from being explosively grown and prepare a desired transfer pattern with high accuracy.
In one aspect of the present invention, there is provided a method for preparing a mask pattern used for forming a desired pattern on a substrate to be exposed, comprising the step of:
effecting correction on design data in connection with a first element to be corrected, the first element allowing a correction amount to be determined depending upon a pattern contained in an area of a predetermined size;
converting the corrected design data to mask writing data; and,
when write processing is done with a writing device in which mask writing data is incorporated, effecting correction in connection with a second element to be corrected which excludes the first element.
It is preferable that the predetermined size (here, the term “size” denotes a size on the substrate to be exposed) be set to be greater than a size of an area over which, upon exposure, an optical effect exceeding a predetermined amount is exerted and be smaller than a size of a highest layer cell in a hierarchical structure included in the design data.
It is preferable that the writing device be comprised of an electron beam writing device and that the correction effected in connection with the second element be performed together with proximity correction of the electron beam writing.
According to the method, the correction is effected on the design data in connection with the first element, the first element allowing a correction amount to be determined depending upon a pattern (especially arrangement or disposition of a pattern) contained in an area of a predetermined size, that is, in a narrower area with a correcting site as a center and, when writing is done by the writing device in which mask writing data is incorporated, correction (correction on a wider area) is effected in connection with the second element to be corrected which excludes the first element.
It is, therefore, possible to suppress a data amount from be largely grown and to prepare a desired transfer pattern, with high accuracy, by transferring a pattern on a wafer with the use of the photomask having a mask pattern obtained by the above-mentioned method.
In another aspect of the present invention, there is provided a method for preparing a mask pattern used for forming a desired pattern on a substrate to be exposed, comprising the steps of:
effecting correction on design data in connection with a first element to be corrected, the first element allowing a correction amount to be determined depending upon a pattern contained in an area of a size corresponding to a size of any desired layer cell between a highest layer cell and a lowest layer cell in a hierarchical structure of the design data;
converting the corrected design data to mask writing data; and,
when write processing is done with a writing device in which mask writing data is incorporated, effecting correction in connection with a second element to be corrected which excludes the first element.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 5792581 (1998-08-01), Ohnumn
patent: 5821014 (1998-10-01), Chen et al.
patent: 5994009 (1999-11-01), Tzu et al.
patent: 6051347 (2000-04-01), Tzu et al.
patent: 10-10701 (1998-01-01), None
John P. Stirniman et al., “Spatial filter models to describe IC lithographic behavior,” SPIE vol. 3051, pp. 469-478, (1998).

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