Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Patent
1998-12-07
2000-05-09
Bowers, Charles
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
438462, 438800, H01L 2176
Patent
active
060603682
ABSTRACT:
This invention is provided to eliminate the optical proximity effect which will occur because of different rates of dimensional change between before and after etching when a plurality of gate materials are etched in a single device. After a to-be-corrected region is extracted, an n.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the n.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be a p.sup.+ -type polysilicon gate layer, thereby correcting the size of the n.sup.+ -type polysilicon gate layer with reference to a correction table for the pattern adjacent to the n.sup.+ -type polysilicon gate layer. After that, a p.sup.+ -type polysilicon gate layer is extracted. Then, the distance is calculated from the p.sup.+ -type polysilicon gate layer to a pattern adjacent thereto which can be an n.sup.+ -type polysilicon gate layer, thereby correcting the size of the p.sup.+ -type polysilicon gate layer with reference to a correction table for the pattern adjacent to the p.sup.+ -type polysilicon gate layer.
REFERENCES:
patent: 5879844 (1999-03-01), Yamamoto et al.
patent: 5995199 (1999-11-01), Shinozaki et al.
L. Liebmann, et al., SPIE vol. 2322, Photomask Technology and Management (1994), pp. 229-238.
Aoyama Hisako
Hashimoto Koji
Inoue Soichi
Kobayashi Sachiko
Yamamoto Kazuko
Bowers Charles
Kabushiki Kaisha Toshiba
Thompson Craig
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