Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2000-08-17
2002-06-25
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S088000, C216S092000, C216S105000, C438S745000, C438S754000, C438S748000
Reexamination Certificate
active
06410442
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a mask-less method of differentially chemically etching the surfaces of recess-patterned copper-based films or layers for providing at least partial planarization thereof. More particularly, the present invention relates to a method for forming a layer of copper or copper-based alloy filling a plurality of spaced apart recesses formed in the surface of a substrate, wherein the exposed upper surface of the layer is substantially coplanar with non-recessed areas of the substrate. Even more particularly, the present invention relates to a method for performing “back-end” metallization of semiconductor high-speed integrated circuit devices having submicron design features and high conductivity interconnect features, which method facilitates full planarization of the metallized surface by chemical-mechanical polishing (CMP), increases manufacturing throughput, and reduces fabrication cost.
BACKGROUND OF THE INVENTION
The present invention relates to a mask-less differential chemical etching method useful in processing copper or copper-based films as part of metallization processing of particular utility in integrated circuit semiconductor device and circuit board manufacture, and is especially adapted for use in processing employing “damascene” (or “in-laid”) technology.
The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-sized (e.g., below 0.18 &mgr;m), low RC time constant metallization patterns, particularly wherein the submicron-sized metallization features such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to microminiaturization.
Semiconductor-devices of the type contemplated herein typically comprise a semiconductor wafer substrate, usually of doped monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced apart metallization layers are electrically interconnected by a vertically oriented conductive plug filling a via hole formed in the dielectric layer separating the layers, while another conductive plug filling a contact area hole establishes electrical contact with an active region, such as a source/drain region, formed in or on the semiconductor substrate. Conductive lines formed in groove or trench-like openings in overlying dielectric layers extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type fabricated according to current technology may comprise five or more levels of such metallization in order to satisfy device geometry and miniaturization requirements.
Electrically conductive films or layers of the type contemplated herein for use in e.g., “backend-end” semiconductor manufacturing technology as required for fabrication of devices as above described typically comprise a metal such as titanium, tungsten, aluminum, chromium, nickel, cobalt, silver, gold, copper, and their alloys. In use, each of the recited metals presents advantages as well as drawbacks. For example, aluminum (Al) is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, in addition to being difficult to deposit by lower cost, lower temperature, more rapid “wet” technology processes such as electrodeposition, step coverage with aluminum is poor when the metallization features are scaled down to submicron size, resulting in decreased reliability of interconnections, high current densities at certain locations, and increased electromigration. In addition, low dielectric constant (“low k”) materials, e.g., polyamides, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with aluminum.
The use of via-plugs filled with tungsten (W) may alleviate several of the above-described problems/drawbacks associated with aluminum. However, most W-based processes are complex and expensive, primarily due to the refractory nature of W. In addition, the relatively high resistivity of W may cause high Joule heating which can undesirably enhance electromigration of aluminum in adjacent wiring. Moreover, W plugs are susceptible to void formation therein and high contact resistance at the interface with the aluminum wiring layer.
Copper (Cu) and Cu-based alloys are particularly attractive for use in large-scale integration (LSI), very large-scale integration (VLSI), and ultra large-scale integration (ULSI) devices requiring multi-level metallization systems for “back-end” processing of the semiconductor wafers on which the devices are based. Cu and Cu-based metallization systems have very low resistivities, i.e., significantly lower than that of W and even lower than those of previously preferred systems utilizing Al or Al-based alloys, as well as significantly higher resistance to electromigration. Moreover, copper and its alloys enjoy a considerable cost advantage over a number of the above-enumerated metals, notably silver and gold. Also, in contrast to Al and the refractory type metals such as W, Ti and Ta, copper and its alloys can be readily deposited at low temperatures in good quality, bright layer form by well-known electroplating techniques, at deposition rates fully compatible with the requirements of device manufacturing throughput.
In addition to convenient, relatively low cost, low temperature, high manufacturing throughput “wet” deposition by electroplating, copper and its alloys are readily amenable to low-cost, high throughput “wet” deposition by “electroless” plating of high quality films for efficiently filling recesses such as vias, contact areas, grooves, and trenches forming interconnection routing. Such electroless plating generally involves the controlled autocatalytic deposition of a film of copper or an alloy thereof on a catalytic surface by interaction with a solution containing at least a copper salt and a chemical reducing agent, whereas electroplating comprises employing electrons supplied to an electrode (i.e., the semiconductor wafer) from an external source (i.e., power supply) for reducing copper ions in solution and depositing the reduced metal atoms obtained thereby on the electrode surface. In either case, a nucleation/seed layer is required for catalytic/deposition (as in electroless plating) or electrolytic deposition (as in electroplating) on the types of substrates contemplated for use herein. Finally, while electroplating requires a continuous nucleation/seed layer, very thin and discontinuous islands of a catalytic metal may be employed with electroless plating.
As indicated above, a commonly employed method for forming “inlaid” metallization patterns such as are required for “back-end” metallization processing of semiconductor wafers employs “damascene” type technology. Generally, in such processing methodology, a recess (i.e., an opening, irrespective of shape or geometry) for forming, e.g., a via hole in a dielectric interlayer, for electrically connecting vertically separated metallization layers, is created in the dielectric interlayer by conventional photolithographic masking and etching techniques, and filled with a metal plug, typically of tungsten. Any excess conductive material (e.g., tungsten) on the surface of the dielectric interlayer is then removed by, e.g., chemical-mechanical polishing (“CMP”) techniques, wherein a moving pad is biased against the surface to be polished, with the interposition of a slurry containing finely-dimensioned abrasive particles (and other ingredients) therebetween. As a result of the CMP processing, the surface of the metal plug filling the recess is coplanar with the surface of
Advanced Micro Devices , Inc.
Powell William A.
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