Mask layout method, and semiconductor device and method for...

Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout

Reexamination Certificate

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C257S786000

Reexamination Certificate

active

07951652

ABSTRACT:
Provided are a mask layout method and a semiconductor device and a method for fabricating the same. The semiconductor device can include a main pattern, a first dummy pattern, and a second dummy pattern. The main pattern can be disposed on a substrate. The first dummy pattern and the second dummy pattern can be disposed around a side of the main pattern. The first dummy pattern can have an inner open region. The second dummy pattern can be disposed on the inner open region of the first dummy pattern, such that the first dummy pattern surrounds the second dummy pattern.

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patent: 2004-254725 (2006-03-01), None

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