Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
2000-03-06
2002-03-12
Rosasco, S. (Department: 1756)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
C378S035000
Reexamination Certificate
active
06355384
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of semiconductor manufacturing and more particularly to a process of forming and using a lithographic mask.
RELATED ART
In the field of semiconductor manufacturing, the ever smaller dimensions required to make state-of-the-art semiconductor devices are rapidly approaching the limits of optical lithographic techniques. Alternatives are being investigated to replace optical lithography once the resolution and depth of focus limits of optical lithography tools are reached. One lithographic technique that is being investigated is projection electron beam (E-beam) lithography. One implementation of electron beam lithography is referred to as scattering with angular limitation in projection electron beam lithography, also referred to as SCALPEL.
SCALPEL masks are basically comprised of a thin, low atomic number membrane material which is fairly transmissive to electrons. On top of these membranes, patterned high atomic number scattering material is formed. In order to fabricate the mask, portions of the silicon substrate are removed to form free-standing membranes. The membranes have width and length dimensions that are approximately 1.1 mm×12.1 mm. Using conventional wet etch processes to form the membranes on a 200 mm silicon substrate having a (100) crystal orientation, only approximately 528 membranes (an array of 8×66 membranes) can be formed. This presently corresponds approximately to a semiconductor die having dimensions of approximately 24×16.5 mm. As semiconductor devices become more complex, chip die dimensions of 25×25 mm will likely be required and an array of 10×100 (1000 membranes) will be needed.
Turning to the drawings,
FIG. 1
is a cross sectional view of a mask
10
used for a SCALPEL process. The mask
10
includes a membrane layer
104
formed overlying a substrate
102
. Typically, the membrane layer
104
is silicon nitride and the substrate
102
is monocrystalline silicon. On one surface of mask
10
, scattering elements
108
are formed overlying membrane layer
104
. On the opposite surface of mask
10
, portions of substrate
102
are removed to form voids
110
and struts
103
. The voids
110
define the regions
109
of membrane layer
104
over which scattering elements
108
may be formed. The scattering elements define the lithographic patterns used for forming the semiconductor devices.
One problem in manufacturing SCALPEL masks is that the formation of struts
103
is typically achieved using a wet etch process that results in a sloped strut sidewall indicated by reference numeral
111
. The sloped sidewall
111
is characteristic of isotropic wet etch processes when etching semiconductor substrates with a (100) crystal orientation. Unfortunately, sloped sidewalls
111
limit the area of membrane layer
104
that can be used to form overlying functional scattering elements. This limitation translates into a corresponding limitation on the maximum die size that can be produced using mask
10
.
To avoid the problems associated with sloped sidewall
111
, one alternative in the formation of SCALPEL masks is to utilize a dry etch process to form the voids
110
in substrate
102
. Unfortunately, however, dry etch processes typically require an etch stop layer formed between substrate
102
and membrane layer
104
. The etch stop layer is typically required because of the lack of sufficient selectivity between substrate
102
and membrane layer
104
associated with dry etch processes. The introduction of additional processing required to fabricate the etch stop layer adds to the cost and complexity of the process required to form the mask. Further, the additional handling can result in an increased number of defects that can limit the yield of the mask formation process. In addition, if it is not subsequently removed, the presence of an etch stop layer during the fabrication of semiconductor devices can limit the throughput due to the loss of transmission of electrons through the additional layers on the mask. Furthermore, the deposition of the etch stop layer must be optimized to ensure that the stress associated with the etch stop layer matches the stress of the membrane layer thereby adding additional complexity to the process. Accordingly, it is highly desirable to implement a mask fabrication process that eliminates the sloped sidewall associated with conventional wet processing while minimizing the additional cost and complexity of the process.
REFERENCES:
patent: 5876881 (1999-03-01), Kawata
patent: 6051346 (2000-04-01), Kornblit et al.
Don L. Kendall et al., “Orientations of the Third Kind: The Coming Of Age Of (110) Silicon”, Elsevier Science Publishers B.V., Amsterdam, 1985, pp. 107-124.
Don L. Kendall, “Vertical Etching Of Silicon At Very High Aspect Ratios”, 1979 by Annual Reviews Inc., Verticle Etching, pp. 373-403.
Kenneth E. Bean, “Anisotropic Etching of Silicon”, 1978 IEEE Transactions On Electron Devices, vol. ED-25, No. 10, pp. 1185-1192.
Ernest Bassous, “Fabrication of Novel Three-Dimensional Microstructures by the Anisotropic Etching of (100) and (110) Silicon”, Oct. 1978 IEEE Transactions of Electron Devices, vol. ED-25,No. 10, pp. 1178-1185.
Dauksher William J.
Mangat Pawitter S.
Lally Joseph
Motorola Inc.
Rodriguez Robert A.
Rosasco S.
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