Mask generation technique for producing an integrated circuit wi

Details Mask generation technique for producing an integrated circuit wi Mask generation technique for producing an integrated circuit wi

1997-10-02

1999-04-13

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257752, 257754, H01L 2348, H01L 2352, H01L 2940

Patent

active

058941681

ABSTRACT:
A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

REFERENCES:
patent: 4916514 (1990-04-01), Nowak
patent: 5328553 (1994-07-01), Poon
patent: 5441915 (1995-08-01), Lee
patent: 5476817 (1995-12-01), Numata
patent: 5621241 (1997-04-01), Jain

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