Image analysis – Applications – Manufacturing or product inspection
Reexamination Certificate
2001-04-09
2004-12-14
Chang, Jon (Department: 2624)
Image analysis
Applications
Manufacturing or product inspection
C382S280000, C382S299000, C382S300000
Reexamination Certificate
active
06831997
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a mask data correction apparatus, a Fourier transformation apparatus, an up sampling apparatus, a down sampling apparatus, a method of manufacturing a transfer mask, and a method of manufacturing a device having a pattern structure. In particular, the invention relates to improvements in increasing efficiency while maintaining accuracy.
2. Description of the Background Art
In recent years, the advance of scale down in large scale integrated circuits (LSIs) has been tremendous. This is owing to the development of micro-lithography technology. Especially, light transfer technology has still been in the center of micro-lithography technology because of high throughput by mass exposure, achievement of optical technology continuously developed over 100 years, and the like.
However, now that the fabrication size of micro-patterns is smaller than the wavelength of an exposure light, it is important to establish the limitation of light transfer technology and to overcome the limitation of resolution and depth of focus. In order to perform such analysis, a technique of performing optical image calculation and a technique of correcting distortion generated from the calculated optical image are now arousing interest.
FIG. 32
is a flow chart illustrating, as one particular example, a procedure of a mask data correction method which was invented by the present inventor and disclosed in Japanese Patent Application Laid-Open No. 8-297692 (1996) (hereinafter referred to as “literature I”).
This method is fully described in literature I and is known in the art, and it will be thus discussed briefly hereinbelow. When process S
90
of this method is started, a circuit design and a layout design are performed (S
91
, S
92
), and initially a layout data is stored in a record medium (S
93
). The layout data defines the shape and hierarchical structure of base elements of a graphic having a hierarchical structure. The layout data is then expanded (S
94
), and a process condition is inputted (S
95
). Thereafter, meshes are formed (S
96
) and an image calculation is performed (S
97
). In comparison of the result of the image calculation with the layout data, a graphic correction is made (S
98
), and a correction data as being the result is outputted (S
99
), thereby completing process S
90
.
When using these techniques, attentions should be given also to degradation of an optical image that is caused by aberration of an optical system. These techniques are fully described in Japanese Patent Application Laid-Open No. 9-167731 (1997) (hereinafter referred to as “literature II”) or No. 10-335224 (1998) (hereinafter referred to as “literature II”), which were invented by the present inventor. In some cases, a long range correlation of full shot level may cause a problem.
In order to perform such evaluation or optimization, it is necessary to check the consistency between the result of calculation and the result of experiment about optical images with regard to various cases. However, the optical image calculation usually requires a large quantity of calculation because, for example, it is required that a mask graphic is subjected to Fourier transformation, followed by inverse Fourier transformation. Thus, numerous proposals for performing Fourier transformation at high speed has been presented. The following methods are generally known.
(1) FFT (Fast Fourier Transformation) which is disclosed in, e.g., “Waveform Data Processing for Scientific Instrumentation” by Shigeo Minami, CQ publishing company;
(2) OCA (Optical Coherent Approximation) which is disclosed in, e.g., Y. C Pali and T. Kailath J. OP Soc. Am A, Vol. 11(1994)2438;
(3) Irregular intervals Fourier transformation which is disclosed in, e.g., E. Barouch, B. Bradie, U. Hollerbach, and S. A. Orszag, J. Vac. Sci. and Technol. B8(1990)1432; E. Barouch, B. Bradie, U. Hollerbach, and S. A. Orszag, Proc. SPIE Vol. 1465(1991)254; and E. Barouch, U. Hollerbach, S. A. Orszag, B. Bradie and M. Peckcrar, IEEE Electron Device Lett., EDL-12(1991)513;
(4) Partial coherent approximation which is disclosed in, e.g., M. Yeung: Proc, Kodak Microelectronics Seminar INTERFACE '85 (KTI Chemicals, Inc, San Diego, 1986) p.115; and M. Yeung: Proc. SPIE Vol. 922(1988)149; and
(5) Massively parallel operation which is disclosed in, e.g., K. Kamon, W. Wakamiya, H. Nagata, K. Moriizumi, T. Miyamoito, Y. Myoi and M. Tanaka; Proc, SPIE Vol. 2512(1995)491; T. Hanawa, K. Kamon, A. Nakae, S. Nakao and K. Moriizumi: Proc, SPIE Vol. 2726(1996)640; and A. Nakae, K. Kamon, T. Hanawa, K. Moriizumi and S. Nakao: Jpn. J. Appl. Phys. Vol.35(1996)6395.
Through these techniques, remarkable high speed has recently been obtained. These techniques, each being extremely effective, have contributed markedly to the innovation of micro-lithography technology. However, a full shot calculation of LSIs cannot be performed satisfactorily even in combination of these, for reasons which are discussed hereinbelow. For instance, in the case of a DRAM of 1G (giga) bit that is under development, a vast number of transistors of 1G are closely disposed longitudinally and transversely to form a memory array. Further, even a logic device has such a configuration that a lot of small-size RAMs are contained. Furthermore, it is assumed that LSIs will be further subjected to high integration in the future.
Conventionally, such a method that a graphic data is processed after a temporal flat expansion (e.g., “dracula” by Cadence Corp.) has usually employed. Whereas in order to handle a large number of graphics, there has recently been developed an apparatus in which operations such as layout verification are performed by utilizing the hierarchical structure of a graphic data (e.g., “hercules” by Arant Corp.; “caliber” by Menter Corp.; and “clover” by Lucent Corp.). In these apparatuses, as shown in
FIG. 33
, high speed processing has been attained by collecting some data at cells
91
, and performing a graphic operation while maintaining the relative disposition of cells and the hierarchical structure. In
FIG. 33
, a plurality of cells
91
are disposed in an image forming region
90
, and a graphic base element
92
is disposed in the cells
91
.
Since these apparatuses can perform simple operation and comparison between graphics at high speed, they are suitable for use in design rule check, logic operation between simple graphics, or sizing.
However, when a certain graphic influence or correlation is exerted widely over a plurality of cells, it is required to expand each element cell. Thus, it is known not only that high speed data processing cannot be attained but also that processing capacity is lowered in some cases.
In application to optical image calculation, a certain graphic influence extends within the coherence length of an optical system. In some cases, micro loading effect in dry etching or proximity effect in mask drawing extends to about 10 &mgr;m. It is therefore necessary to calculate the state that graphic elements interfere or influence with each other. It can be said that such correlation state calculation is rather essential in a variety of process simulations including lithography. Since the above-mentioned optical coherency or various proximity effects usually extend over a plurality of cells, it has conventionally been necessary to expand all the cells for evaluation. As a result, even if the hierarchical data is used in proximity correction calculation, it is finally required to expand all the cells. This makes it impossible to sufficiently exhibit the effectiveness of hierarchical processing.
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the disadvantages in the prior art by providing a mask data correction apparatus, a Fourier transformation apparatus, an up sampling apparatus, a down sampling apparatus, a method of manufacturing a transfer mask, and a method of manufacturing a device having a pattern structure, each of which is capable of increasing processing
Chang Jon
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
Tucker Wesley
LandOfFree
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