Active solid-state devices (e.g. – transistors – solid-state diode – Incoherent light emitter structure – With reflector – opaque mask – or optical element integral...
Reexamination Certificate
2002-02-11
2003-12-30
Nhu, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Incoherent light emitter structure
With reflector, opaque mask, or optical element integral...
C257S091000
Reexamination Certificate
active
06670646
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to a patterning mask and method.
BACKGROUND OF THE INVENTION
Semiconductors are widely used for integrated circuits for electronic applications, including radios, televisions, cellular phones, and personal computing devices, as examples. Such integrated circuits (IC's) typically include multiple transistors fabricated in single crystal silicon. It is common for there to be millions of semiconductor devices on a single semiconductor product. Many integrated circuits now include multiple levels of metallization for interconnections.
Semiconductor device fabrication involves depositing or forming metallization, dielectric, and active component layers, as examples, on a semiconductor wafer. Each layer must be patterned with a desired pattern in order for the semiconductor devices to function properly. A patterning process typically involves depositing a photoresist that may comprise an organic polymer, for example, over a semiconductor wafer layer. The photoresist is exposed through a mask to transfer the pattern of the mask to the photoresist. Either exposed or unexposed portions of the photoresist are removed during subsequent development processes, depending on whether a positive or negative lithographic resist process is used. The photoresist portions remaining on the semiconductor wafer surface shield the top wafer surface during an etch process to leave the top semiconductor wafer layer residing in regions where photoresist remain.
A prior art apparatus
10
for patterning the surface of a semiconductor wafer
30
is shown in
FIG. 1. A
stage
12
is adapted to support a semiconductor wafer
30
. The stage
12
may be adapted to move the entire wafer
30
from position to position in order to expose portions of the wafer
30
surface during the patterning process. The stage
12
may be mounted on a base, not shown. The stage
12
is adapted to securely hold the wafer
30
in place. A lens
20
is disposed above the wafer
30
. Lens
20
typically comprises a demagnification lens that reduces the image transferred to the wafer
30
by 4-5×, for example. Alternatively, no lens
20
may be required if a 1:1 ratio magnification scheme is used for transferring the pattern from the mask
18
to the wafer
30
. A mask
18
having the desired pattern to be transferred to the wafer
30
is disposed above lens
20
. A light or energy source
16
is disposed above mask
18
, as shown.
To pattern the wafer
30
, the light source
16
which may comprise a laser or ultraviolet light, for example, is illuminated. The light passes through the mask
18
, through demagnification lens
20
, and exposes portions of the top surface of the semiconductor wafer
30
.
There are various types of exposure tools that function similarly to the apparatus
10
described and illustrated in FIG.
1
. In a step and repeat apparatus, the mask
18
pattern is transferred onto a section of the wafer
30
at a time, and a stage
12
moves the wafer
30
from point to point, exposing the wafer
30
surface in a plurality of steps. An alternative apparatus used to pattern and expose a wafer
30
surface is known as a step and scan apparatus, for example.
FIG. 2
illustrates a top view of a mask
18
having a pattern including transparent regions, holes or apertures
22
therein. A portion of a wafer
30
top surface is also shown, having much smaller dimensions than the mask
18
due to demagnification. Wafer regions
26
represent exposed (or unexposed) patterned portions of the semiconductor wafer
30
surface after patterning the wafer
30
using the mask
18
.
The pattern shown in
FIG. 2
may represent a pattern for deep trenches used in memory cells of semiconductor devices, for example. Deep trench printing is a challenge for lithographers due to limited process latitude and resolution of prior art apparatuses and methods. Due to practical process window constraints, it is difficult to further reduce the current deep trench critical dimension (CD) targets.
Another problem with prior art lithography masks and processes is that a larger mask
18
is typically used than the desired pattern on a wafer
30
. Due to resolution and diffraction of the light through the mask
18
, the pattern transferred to the wafer
30
is distorted, and therefore a greater than one-to-one ratio is used to transfer the desired image or pattern. However, it is desirable in the art to have a one-to-one relationship between the pattern on the mask
18
and the pattern on the wafer
30
, which would require no demagnification in the lens
20
.
Furthermore, a transfer problem referred to as line shortening may occur when the mask
18
pattern is transferred to the semiconductor wafer
30
surface. Line shortening is typically more problematic for small feature sizes; for example, the length L of
FIG. 2
design target may be difficult to achieve because of line shortening.
Some prior art methods for improving lithography of patterns with narrow geometries include dense optical proximity correction (OPC) and phase shift masks (PSM). OPC helps compensate for lost light to ensure that the precise patterns are formed on a semiconductor wafer. For example, without OPC, a rectangle produces a pattern on a semiconductor wafer that appears oval because light tends to round on the edges. OPC is used to correct this phenomenon by adding tiny serifs, or lines, to the corners to ensure that the corners are not rounded, or moving a feature edge so wafer features are sized more accurately. Phase shift masks alter the phase of light passing through the photomask, and permit improved depth of focus and resolution on the wafer. Phase shifting helps reduce the distortion of line resolution of wafer surface irregularities.
What is needed in the art is a semiconductor wafer patterning mask and method that alleviates mask demagnification requirements and line shortening problems found in prior art methods and masks.
SUMMARY OF THE INVENTION
Embodiments of the present invention achieve technical advantages as a method and apparatus for patterning the surface of a semiconductor wafer.
Disclosed is a method of manufacturing a semiconductor wafer patterning mask, the method comprising providing a transparent substrate, forming an opaque material over the substrate, and forming a pattern in the opaque material, where the pattern includes a plurality of apertures and an assist line positioned between at least two of the apertures.
Also disclosed is a semiconductor wafer patterning mask, comprising a transparent substrate, and an opaque material disposed over the substrate, the opaque material comprising a pattern including a plurality of apertures, wherein an assist line is coupled between at least two of the apertures.
Further disclosed is a semiconductor device patterned with a semiconductor wafer patterning mask, comprising a transparent substrate, and an opaque material disposed over the substrate, the opaque material comprising a pattern including a plurality of apertures, wherein an assist line is coupled between at least two of the apertures.
Advantages of the embodiments of the invention include increased depth of focus (DOF) and increased exposure latitude. Resolution is enhanced, and line shortening is reduced. Furthermore, printing elliptical deep trenches is achievable in accordance with embodiments of the present invention. Smaller deep trench critical dimensions are made possible with the use of assist lines. The need for a bias or demagnification of the mask pattern with respect to the wafer may be eliminated. The need for a test mask may also be eliminated in accordance with embodiments of the present invention.
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patent: 5242770 (1993-09-01), Chen et al.
patent: 5256505 (1993-10-01), Chen et al.
patent: 5316896 (1994-05-01), Fukuda et al.
patent: 5397663 (1995-03-01), Uesawa et al.
patent: 5416722 (1995-05-01), Edwards
patent: 5447810 (1995-09-01), Chen et al.
patent: 5468578 (1995-11-01), Rolfson
pa
Butt Shahid
Gutmann Alois
Lu Zhijian
Infineon - Technologies AG
Slater & Matsil L.L.P.
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